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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2018-09-15 15:16:21 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2018-09-15 15:16:21 -0700 |
| commit | c9059fc7d0395e895520dc37019486339b43e3c9 (patch) | |
| tree | 2c021c698e9df79467217aa60191f1434ba3f455 | |
| parent | e7fe046e571aa007fcb2e10af0a097b839bfef0c (diff) | |
| download | nextpnr-c9059fc7d0395e895520dc37019486339b43e3c9.tar.gz nextpnr-c9059fc7d0395e895520dc37019486339b43e3c9.tar.bz2 nextpnr-c9059fc7d0395e895520dc37019486339b43e3c9.zip | |
[ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNORE
| -rw-r--r-- | ice40/arch.cc | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index 3983a24e..28d20adb 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -866,15 +866,22 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, Id return TMG_COMB_INPUT; if (port == id_COUT || port == id_LO) return TMG_COMB_OUTPUT; - if (cell->lcInfo.dffEnable) { - clockPort = id_CLK; - if (port == id_O) + if (port == id_O) { + // LCs with no inputs are constant drivers + if (cell->lcInfo.inputCount == 0) + return TMG_IGNORE; + if (cell->lcInfo.dffEnable) { + clockPort = id_CLK; return TMG_REGISTER_OUTPUT; + } else - return TMG_REGISTER_INPUT; - } else { - if (port == id_O) return TMG_COMB_OUTPUT; + } + else { + if (cell->lcInfo.dffEnable) { + clockPort = id_CLK; + return TMG_REGISTER_INPUT; + } else return TMG_COMB_INPUT; } |