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author | David Shah <davey1576@gmail.com> | 2018-08-02 16:02:43 +0200 |
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committer | David Shah <davey1576@gmail.com> | 2018-08-02 16:02:51 +0200 |
commit | a7269a685ec57f855f0c46b0adbd6aa8e9a03843 (patch) | |
tree | 04b48053e771c51d002390c79990b88af2367743 | |
parent | c0aaac8dfab08f753bdb1f4d4e0315b65bbaf98a (diff) | |
download | nextpnr-a7269a685ec57f855f0c46b0adbd6aa8e9a03843.tar.gz nextpnr-a7269a685ec57f855f0c46b0adbd6aa8e9a03843.tar.bz2 nextpnr-a7269a685ec57f855f0c46b0adbd6aa8e9a03843.zip |
ice40: Use real cell timings
Signed-off-by: David Shah <davey1576@gmail.com>
-rw-r--r-- | ice40/arch.cc | 39 | ||||
-rw-r--r-- | ice40/arch.h | 2 | ||||
-rw-r--r-- | ice40/chipdb.py | 11 |
3 files changed, 24 insertions, 28 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index 2867f591..eff1d9b9 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -834,28 +834,23 @@ std::vector<GraphicElement> Arch::getDecalGraphics(DecalId decal) const bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const { - if (cell->type == id_icestorm_lc) { - if ((fromPort == id_i0 || fromPort == id_i1 || fromPort == id_i2 || fromPort == id_i3) && - (toPort == id_o || toPort == id_lo)) { - delay.delay = 450; - return true; - } else if (fromPort == id_cin && toPort == id_cout) { - delay.delay = 120; - return true; - } else if (fromPort == id_i1 && toPort == id_cout) { - delay.delay = 260; - return true; - } else if (fromPort == id_i2 && toPort == id_cout) { - delay.delay = 230; - return true; - } else if (fromPort == id_clk && toPort == id_o) { - delay.delay = 540; - return true; - } - } else if (cell->type == id_icestorm_ram) { - if (fromPort == id_rclk) { - delay.delay = 2140; - return true; + BelType type = belTypeFromId(cell->type); + for (int i = 0; i < chip_info->num_timing_cells; i++) { + const auto &tc = chip_info->cell_timing[i]; + if (tc.type == type) { + PortPin fromPin = portPinFromId(fromPort); + PortPin toPin = portPinFromId(toPort); + for (int j = 0; j < tc.num_paths; j++) { + const auto &path = tc.path_delays[j]; + if (path.from_port == fromPin && path.to_port == toPin) { + if (fast_part) + delay.delay = path.fast_delay; + else + delay.delay = path.slow_delay; + return true; + } + } + break; } } return false; diff --git a/ice40/arch.h b/ice40/arch.h index cf63a993..e67f2aa9 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -180,7 +180,7 @@ NPNR_PACKED_STRUCT(struct CellPathDelayPOD { }); NPNR_PACKED_STRUCT(struct CellTimingPOD { - BelType type; + int32_t type; int32_t num_paths; RelPtr<CellPathDelayPOD> path_delays; }); diff --git a/ice40/chipdb.py b/ice40/chipdb.py index 842ae2a2..3f9f4e65 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -666,14 +666,14 @@ def add_bel_ec(ec): cell_timings = {} tmport_to_portpin = { "posedge:clk": "CLK", - "ce": "CE", + "ce": "CEN", "sr": "SR", "in0": "I0", "in1": "I1", "in2": "I2", "in3": "I3", "carryin": "CIN", - "carrout": "COUT", + "carryout": "COUT", "lcout": "O", "ltout": "LO", "posedge:RCLK": "RCLK", @@ -711,8 +711,8 @@ def add_cell_timingdata(bel_type, timing_cell, fast_db, slow_db): cell_timings[bel_type] = timing_entries add_cell_timingdata("ICESTORM_LC", "LogicCell40", fast_timings, slow_timings) -add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings) - +if dev_name != "384": + add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings) if dev_name == "5k": add_cell_timingdata("SPRAM", "SB_SPRAM256KA", fast_timings, slow_timings) @@ -1154,6 +1154,7 @@ bba.u32(len(pipinfo), "num_pips") bba.u32(len(switchinfo), "num_switches") bba.u32(len(extra_cell_config), "num_belcfgs") bba.u32(len(packageinfo), "num_packages") +bba.u32(len(cell_timings), "num_timing_cells") bba.r("bel_data_%s" % dev_name, "bel_data") bba.r("wire_data_%s" % dev_name, "wire_data") bba.r("pip_data_%s" % dev_name, "pip_data") @@ -1161,6 +1162,6 @@ bba.r("tile_grid_%s" % dev_name, "tile_grid") bba.r("bits_info_%s" % dev_name, "bits_info") bba.r("bel_config_%s" % dev_name if len(extra_cell_config) > 0 else None, "bel_config") bba.r("package_info_%s" % dev_name, "packages_data") -bba.r("cell_timing_%s" % dev_name, "cell_timing") +bba.r("cell_timings_%s" % dev_name, "cell_timing") bba.pop() |