Merge branch 'q3k/pll-pads' into 'master'

ice40: PLL40_*_PAD support

See merge request SymbioticEDA/nextpnr!21

4 files changed, 96 insertions, 13 deletions

diff --git a/common/placer1.cc b/common/placer1.cc
index f713fb88..4659da11 100644
--- a/common/placer1.cc
+++ b/common/placer1.cc
@@ -94,7 +94,13 @@ class SAPlacer
                 BelType bel_type = ctx->getBelType(bel);
                 if (bel_type != ctx->belTypeFromId(cell->type)) {
                     log_error("Bel \'%s\' of type \'%s\' does not match cell "
-                              "\'%s\' of type \'%s\'",
+                              "\'%s\' of type \'%s\'\n",
+                              loc_name.c_str(), ctx->belTypeToId(bel_type).c_str(ctx), cell->name.c_str(ctx),
+                              cell->type.c_str(ctx));
+                }
+                if (!ctx->isValidBelForCell(cell, bel)) {
+                    log_error("Bel \'%s\' of type \'%s\' is not valid for cell "
+                              "\'%s\' of type \'%s\'\n",
                               loc_name.c_str(), ctx->belTypeToId(bel_type).c_str(ctx), cell->name.c_str(ctx),
                               cell->type.c_str(ctx));
                 }
diff --git a/ice40/arch.h b/ice40/arch.h
index 3aec25a2..bd937371 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -739,6 +739,18 @@ struct Arch : BaseCtx
     IdString id_cen, id_clk, id_sr;
     IdString id_i0, id_i1, id_i2, id_i3;
     IdString id_dff_en, id_neg_clk;
+
+    // -------------------------------------------------
+    BelPin getIOBSharingPLLPin(BelId pll, PortPin pll_pin) const
+    {
+        auto wire = getBelPinWire(pll, pll_pin);
+        for (auto src_bel : getWireBelPins(wire)) {
+            if (getBelType(src_bel.bel) == TYPE_SB_IO && src_bel.pin == PIN_D_IN_0) {
+                return src_bel;
+            }
+        }
+        NPNR_ASSERT_FALSE("Expected PLL pin to share an output with an SB_IO D_IN_{0,1}");
+    }
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 59e1807d..b3404d6c 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -124,12 +124,16 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
         }
         // Is there a PLL that shares this IO buffer?
         if (pll_bel.index != -1) {
+            auto pll_cell = getBoundBelCell(pll_bel);
             // Is a PLL placed in this PLL bel?
-            if (!checkBelAvail(pll_bel)) {
+            if (pll_cell != IdString()) {
                 // Is the shared port driving a net?
-                auto pll_cell = getBoundBelCell(pll_bel);
                 auto pi = cells.at(pll_cell)->ports[portPinToId(pll_bel_pin)];
                 if (pi.net != nullptr) {
+                    // Are we perhaps a PAD INPUT Bel that can be placed here?
+                    if (cells.at(pll_cell)->attrs[id("BEL_PAD_INPUT")] == getBelName(bel).str(this)) {
+                        return true;
+                    }
                     return false;
                 }
             }
diff --git a/ice40/pack.cc b/ice40/pack.cc
index b4f711f3..91dcf846 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -550,13 +550,13 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
     NPNR_ASSERT(port.net != nullptr);
 
     // Create pass-through LUT.
-    std::unique_ptr<CellInfo> pt =
-            create_ice_cell(ctx, ctx->id("ICESTORM_LC"), ci->name.str(ctx) + "$nextpnr_ice40_pack_pll_lc");
-    pt->params[ctx->id("LUT_INIT")] = "255"; // output is always I3
+    std::unique_ptr<CellInfo> pt = create_ice_cell(ctx, ctx->id("ICESTORM_LC"),
+                                                   ci->name.str(ctx) + "$nextpnr_" + portId.str(ctx) + "_lut_through");
+    pt->params[ctx->id("LUT_INIT")] = "65280"; // output is always I3
 
     // Create LUT output net.
     std::unique_ptr<NetInfo> out_net = std::unique_ptr<NetInfo>(new NetInfo);
-    out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_ice40_pack_pll_net");
+    out_net->name = ctx->id(ci->name.str(ctx) + "$nextnr_" + portId.str(ctx) + "_lut_through_net");
     out_net->driver.cell = pt.get();
     out_net->driver.port = ctx->id("O");
     pt->ports.at(ctx->id("O")).net = out_net.get();
@@ -647,16 +647,14 @@ static void pack_special(Context *ctx)
             }
             new_cells.push_back(std::move(packed));
         } else if (is_sb_pll40(ctx, ci)) {
+            bool is_pad = is_sb_pll40_pad(ctx, ci);
+            bool is_core = !is_pad;
+
             std::unique_ptr<CellInfo> packed =
                     create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL");
+            packed->attrs[ctx->id("TYPE")] = ci->type.str(ctx);
             packed_cells.insert(ci->name);
 
-            if (is_sb_pll40_pad(ctx, ci)) {
-                // TODO(q3k): Implement these after checking their behaviour on
-                // a board with exposed 'clock pads'.
-                log_error("SB_PLL40_*_PAD cells are not supported yet.\n");
-            }
-
             for (auto attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
             for (auto param : ci->params)
@@ -672,6 +670,8 @@ static void pack_special(Context *ctx)
                                                                   : feedback_path == "EXTERNAL" ? "6" : feedback_path;
             packed->params[ctx->id("PLLTYPE")] = std::to_string(sb_pll40_type(ctx, ci));
 
+            NetInfo *pad_packagepin_net = nullptr;
+
             for (auto port : ci->ports) {
                 PortInfo &pi = port.second;
                 std::string newname = pi.name.str(ctx);
@@ -685,6 +685,22 @@ static void pack_special(Context *ctx)
                     newname = "PLLOUT_B";
                 if (pi.name == ctx->id("PLLOUTCORE"))
                     newname = "PLLOUT_A";
+
+                if (pi.name == ctx->id("PACKAGEPIN")) {
+                    if (!is_pad) {
+                        log_error("  PLL '%s' has a PACKAGEPIN but is not a PAD PLL", ci->name.c_str(ctx));
+                    } else {
+                        // We drop this port and instead place the PLL adequately below.
+                        pad_packagepin_net = port.second.net;
+                        NPNR_ASSERT(pad_packagepin_net != nullptr);
+                        continue;
+                    }
+                }
+                if (pi.name == ctx->id("REFERENCECLK")) {
+                    if (!is_core)
+                        log_error("  PLL '%s' has a REFERENCECLK but is not a CORE PLL", ci->name.c_str(ctx));
+                }
+
                 replace_port(ci, ctx->id(pi.name.c_str(ctx)), packed.get(), ctx->id(newname));
             }
 
@@ -696,6 +712,42 @@ static void pack_special(Context *ctx)
                 for (auto bel : ctx->getBels()) {
                     if (ctx->getBelType(bel) != TYPE_ICESTORM_PLL)
                         continue;
+
+                    // A PAD PLL must have its' PACKAGEPIN on the SB_IO that's shared
+                    // with PLLOUT_A.
+                    if (is_pad) {
+                        auto pll_sb_io_belpin = ctx->getIOBSharingPLLPin(bel, PIN_PLLOUT_A);
+                        NPNR_ASSERT(pad_packagepin_net != nullptr);
+                        auto pll_packagepin_driver = pad_packagepin_net->driver;
+                        NPNR_ASSERT(pll_packagepin_driver.cell != nullptr);
+                        if (pll_packagepin_driver.cell->type != ctx->id("SB_IO")) {
+                            log_error("  PLL '%s' has a PACKAGEPIN driven by "
+                                      "an %s, should be directly connected to an input SB_IO\n",
+                                      ci->name.c_str(ctx), pll_packagepin_driver.cell->type.c_str(ctx));
+                        }
+
+                        auto packagepin_cell = pll_packagepin_driver.cell;
+                        auto packagepin_bel_name = packagepin_cell->attrs.find(ctx->id("BEL"));
+                        if (packagepin_bel_name == packagepin_cell->attrs.end()) {
+                            log_error("  PLL '%s' PACKAGEPIN SB_IO '%s' is unconstrained\n", ci->name.c_str(ctx),
+                                      packagepin_cell->name.c_str(ctx));
+                        }
+                        auto packagepin_bel = ctx->getBelByName(ctx->id(packagepin_bel_name->second));
+                        if (pll_sb_io_belpin.bel != packagepin_bel) {
+                            log_error("  PLL '%s' PACKAGEPIN is connected to pin %s, can only be pin %s\n",
+                                      ci->name.c_str(ctx), ctx->getBelPackagePin(packagepin_bel).c_str(),
+                                      ctx->getBelPackagePin(pll_sb_io_belpin.bel).c_str());
+                        }
+                        if (pad_packagepin_net->users.size() != 1) {
+                            log_error("  PLL '%s' clock input '%s' can only drive PLL\n", ci->name.c_str(ctx),
+                                      pad_packagepin_net->name.c_str(ctx));
+                        }
+                        // Set an attribute about this PLL's PAD SB_IO.
+                        packed->attrs[ctx->id("BEL_PAD_INPUT")] = packagepin_bel_name->second;
+                        // Remove the connection from the SB_IO to the PLL.
+                        packagepin_cell->ports.erase(pll_packagepin_driver.port);
+                    }
+
                     log_info("  constrained '%s' to %s\n", packed->name.c_str(ctx), ctx->getBelName(bel).c_str(ctx));
                     packed->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
                     pll_bel = bel;
@@ -706,6 +758,15 @@ static void pack_special(Context *ctx)
                 }
             }
 
+            // Delete the original PACKAGEPIN net if needed.
+            if (pad_packagepin_net != nullptr) {
+                for (auto user : pad_packagepin_net->users) {
+                    user.cell->ports.erase(user.port);
+                }
+                ctx->nets.erase(pad_packagepin_net->name);
+                pad_packagepin_net = nullptr;
+            }
+
             // The LOCK signal on iCE40 PLLs goes through the neigh_op_bnl_1 wire.
             // In practice, this means the LOCK signal can only directly reach LUT
             // inputs.