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| author | David Shah <davey1576@gmail.com> | 2018-07-10 14:02:01 +0200 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-07-11 10:42:09 +0200 |
| commit | 9a2e8caf1c40ede0922a9c492e5c774ec66e61d3 (patch) | |
| tree | fc7fb5873d7252ca19859d7f4f9d57f20d007ede | |
| parent | 1830c9372e9bb959cb886c8271d64778550a7ebb (diff) | |
| download | nextpnr-9a2e8caf1c40ede0922a9c492e5c774ec66e61d3.tar.gz nextpnr-9a2e8caf1c40ede0922a9c492e5c774ec66e61d3.tar.bz2 nextpnr-9a2e8caf1c40ede0922a9c492e5c774ec66e61d3.zip | |
ecp5: Buttons working
Signed-off-by: David Shah <davey1576@gmail.com>
| -rw-r--r-- | ecp5/synth/blinky.v | 15 | ||||
| -rw-r--r-- | ecp5/synth/ulx3s.v | 2 | ||||
| -rwxr-xr-x | ecp5/trellis_import.py | 2 |
3 files changed, 14 insertions, 5 deletions
diff --git a/ecp5/synth/blinky.v b/ecp5/synth/blinky.v index bda627cc..11ba5e4c 100644 --- a/ecp5/synth/blinky.v +++ b/ecp5/synth/blinky.v @@ -1,7 +1,7 @@ module top(input clk_pin, output [3:0] led_pin, output gpio0_pin); wire clk; - wire [3:0] led; + wire [7:0] led; wire gpio0; @@ -17,16 +17,25 @@ module top(input clk_pin, output [3:0] led_pin, output gpio0_pin); (* BEL="X0/Y26/PIOC" *) (* IO_TYPE="LVCMOS33" *) TRELLIS_IO #(.DIR("OUTPUT")) led_buf_3 (.B(led_pin[3]), .I(led[3])); + (* BEL="X0/Y26/PIOB" *) (* IO_TYPE="LVCMOS33" *) + TRELLIS_IO #(.DIR("OUTPUT")) led_buf_4 (.B(led_pin[4]), .I(led[4])); + (* BEL="X0/Y32/PIOD" *) (* IO_TYPE="LVCMOS33" *) + TRELLIS_IO #(.DIR("OUTPUT")) led_buf_5 (.B(led_pin[5]), .I(led[5])); + (* BEL="X0/Y26/PIOD" *) (* IO_TYPE="LVCMOS33" *) + TRELLIS_IO #(.DIR("OUTPUT")) led_buf_6 (.B(led_pin[6]), .I(led[6])); + (* BEL="X0/Y29/PIOD" *) (* IO_TYPE="LVCMOS33" *) + TRELLIS_IO #(.DIR("OUTPUT")) led_buf_7 (.B(led_pin[7]), .I(led[7])); + (* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *) TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0)); - reg [25:0] ctr = 0; + reg [27:0] ctr = 0; always@(posedge clk) ctr <= ctr + 1'b1; - assign led = ctr[25:22]; + assign led = ctr[27:20]; // Tie GPIO0, keep board from rebooting TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0)); diff --git a/ecp5/synth/ulx3s.v b/ecp5/synth/ulx3s.v index 486366fa..08f6e65b 100644 --- a/ecp5/synth/ulx3s.v +++ b/ecp5/synth/ulx3s.v @@ -3,7 +3,7 @@ module top(input a_pin, output led_pin, output led2_pin, output gpio0_pin); wire a; wire led, led2; wire gpio0; - (* BEL="X90/Y65/PIOB" *) (* IO_TYPE="LVCMOS33" *) + (* BEL="X4/Y71/PIOA" *) (* IO_TYPE="LVCMOS33" *) TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a)); (* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *) TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led)); diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 6ff929f7..60e48844 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -154,7 +154,7 @@ def add_bels(chip, x, y): num_slices = 4 elif "PICL0" in tt or "PICR0" in tt: num_pios = 4 - elif "PIOT0" in tt or "PIOB0" in tt: + elif "PIOT0" in tt or ("PICB0" in tt and "SPICB" not in tt): num_pios = 2 for i in range(num_slices): add_slice(x, y, i) |