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authorgatecat <gatecat@ds0.me>2022-03-15 18:54:18 +0000
committerGitHub <noreply@github.com>2022-03-15 18:54:18 +0000
commit81b48b414bf8dd9c2c660864225491d69a692d14 (patch)
tree63d7fd61c9172710c1e129a72b4bc33864339678
parent6ed625be8e4e4f6f1ec7d74d4180b4ed60c96f9d (diff)
parent1cc71c7846463c401b63c15cf7da3c674b50269e (diff)
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Merge pull request #947 from antmicro/dcc_enhancements
nexus: DCC support fixups
-rw-r--r--nexus/arch.cc8
-rw-r--r--nexus/fasm.cc12
2 files changed, 20 insertions, 0 deletions
diff --git a/nexus/arch.cc b/nexus/arch.cc
index cb8cacf8..0241e832 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -546,6 +546,14 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
if (type == TMG_REGISTER_INPUT || type == TMG_REGISTER_OUTPUT)
clockInfoCount = 1;
return type;
+ } else if (cell->type == id_DCC) {
+ if (port == id_CLKI)
+ return TMG_CLOCK_INPUT;
+ else if (port == id_CLKO)
+ return TMG_GEN_CLOCK;
+ else if (port == id_CE)
+ return TMG_COMB_INPUT;
+ return TMG_IGNORE;
}
return TMG_IGNORE;
}
diff --git a/nexus/fasm.cc b/nexus/fasm.cc
index c460e14b..c8404587 100644
--- a/nexus/fasm.cc
+++ b/nexus/fasm.cc
@@ -526,6 +526,16 @@ struct NexusFasmWriter
write_cell_muxes(cell);
pop(2);
}
+ // Write config for DCC
+ void write_dcc(const CellInfo *cell)
+ {
+ BelId bel = cell->bel;
+ push_tile(bel.tile);
+ push_belname(bel);
+ write_bit("DCCEN.1"); // Explicit DCC cell implies a clock buffer
+ write_cell_muxes(cell);
+ pop(2);
+ }
// Write config for an OXIDE_EBR cell
void write_bram(const CellInfo *cell)
{
@@ -927,6 +937,8 @@ struct NexusFasmWriter
write_dphy(ci);
else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC)
write_iol(ci);
+ else if (ci->type == id_DCC)
+ write_dcc(ci);
blank();
}
// Handle DCC route-throughs