First pass at data structures for hierarchy

Signed-off-by: David Shah <dave@ds0.me>

2 files changed, 31 insertions, 2 deletions

diff --git a/common/nextpnr.h b/common/nextpnr.h
index 3fce97a2..ceea2088 100644
--- a/common/nextpnr.h
+++ b/common/nextpnr.h
@@ -387,7 +387,7 @@ struct ClockConstraint;
 
 struct NetInfo : ArchNetInfo
 {
-    IdString name;
+    IdString name, hierpath;
     int32_t udata = 0;
 
     PortRef driver;
@@ -423,7 +423,7 @@ struct PortInfo
 
 struct CellInfo : ArchCellInfo
 {
-    IdString name, type;
+    IdString name, type, hierpath;
     int32_t udata;
 
     std::unordered_map<IdString, PortInfo> ports;
@@ -527,6 +527,28 @@ struct TimingConstraint
     std::unordered_set<TimingConstrObjectId> to;
 };
 
+// Represents the contents of a non-leaf cell in a design
+// with hierarchy
+
+struct HierachicalPort
+{
+    IdString name;
+    PortType dir;
+    std::vector<IdString> nets;
+    int offset;
+    bool upto;
+};
+
+struct HierachicalCell
+{
+    IdString name, type, parent, fullpath;
+    // Name inside cell instance -> global name
+    std::unordered_map<IdString, IdString> leaf_cells, nets;
+    std::unordered_map<IdString, HierachicalPort> ports;
+    // Name inside cell instance -> global name
+    std::unordered_map<IdString, IdString> hier_cells;
+};
+
 inline bool operator==(const std::pair<const TimingConstrObjectId, TimingConstraint *> &a,
                        const std::pair<TimingConstrObjectId, TimingConstraint *> &b)
 {
@@ -620,6 +642,11 @@ struct BaseCtx
     std::unordered_map<IdString, std::unique_ptr<NetInfo>> nets;
     std::unordered_map<IdString, std::unique_ptr<CellInfo>> cells;
 
+    // Hierarchical (non-leaf) cells by full path
+    std::unordered_map<IdString, HierachicalCell> hierarchy;
+    // This is the root of the above structure
+    IdString top_module;
+
     // Aliases for nets, which may have more than one name due to assignments and hierarchy
     std::unordered_map<IdString, IdString> net_aliases;
 
diff --git a/docs/netlist.md b/docs/netlist.md
index 0f9a8969..8886e4f8 100644
--- a/docs/netlist.md
+++ b/docs/netlist.md
@@ -19,6 +19,7 @@ Other structures used by these basic structures include:
 `CellInfo` instances have the following fields:
 
  - `name` and `type` are `IdString`s containing the instance name, and type
+ - `hierpath` is name of the hierarchical cell containing the instance, for designs with hierarchy
  - `ports` is a map from port name `IdString` to `PortInfo` structures for each cell port
  - `bel` and `belStrength` contain the ID of the Bel the cell is placed onto; and placement strength of the cell; if placed. Placement/ripup should always be done by `Arch::bindBel` and `Arch::unbindBel` rather than by manipulating these fields.
  - `params` and `attrs` store parameters and attributes - from the input JSON or assigned in flows to add metadata - by mapping from parameter name `IdString` to `Property`.
@@ -34,6 +35,7 @@ Other structures used by these basic structures include:
 `NetInfo` instances have the following fields:
 
  - `name` is the IdString name of the net - for nets with multiple names, one name is chosen according to a set of rules by the JSON frontend
+ - `hierpath` is name of the hierarchical cell containing the instance, for designs with hierarchy
  - `driver` refers to the source of the net using `PortRef`; `driver.cell == nullptr` means that the net is undriven. Nets must have zero or one driver only. The corresponding cell port must be an output and its `PortInfo::net` must refer back to this net.
  - `users` contains a list of `PortRef` references to sink ports on the net. Nets can have zero or more sinks. Each corresponding cell port must be an input or inout; and its `PortInfo::net` must refer back to this net.
  - `wires` is a map that stores the routing tree of a net, if the net is routed.