ecp5: Infrastructure for BRAM bitstream gen

Signed-off-by: David Shah <dave@ds0.me>

3 files changed, 56 insertions, 0 deletions

diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index 296ea753..dad9da66 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -20,6 +20,7 @@
 #include "bitstream.h"
 
 #include <fstream>
+#include <regex>
 #include <streambuf>
 
 #include "config.h"
@@ -61,6 +62,30 @@ static std::vector<bool> int_to_bitvector(int val, int size)
     return bv;
 }
 
+// Tie a wire using the CIB ties
+static void tie_cib_signal(Context *ctx, ChipConfig &cc, WireId wire, bool value)
+{
+    static const std::regex cib_re("J([A-D]|CE|LSR|CLK)[0-7]");
+    WireId cibsig = wire;
+    std::string basename = ctx->getWireBasename(wire).str(ctx);
+
+    while (!std::regex_match(basename, cib_re)) {
+        auto uphill = ctx->getPipsUphill(cibsig);
+        NPNR_ASSERT(uphill.begin() != uphill.end()); // At least one uphill pip
+        auto iter = uphill.begin();
+        cibsig = ctx->getPipSrcWire(*iter);
+        ++iter;
+        NPNR_ASSERT(!(iter != uphill.end())); // Exactly one uphill pip
+    }
+    for (const auto &tile : ctx->getTilesAtLocation(cibsig.location.y, cibsig.location.x)) {
+        if (tile.second.substr(0, 3) == "CIB" || tile.second.substr(0, 4) == "VCIB") {
+            cc.tiles[tile.first].add_enum("CIB." + basename + "MUX", value ? "1" : "0");
+            return;
+        }
+    }
+    NPNR_ASSERT_FALSE("CIB tile not found at location");
+}
+
 // Get the PIO tile corresponding to a PIO bel
 static std::string get_pio_tile(Context *ctx, BelId bel)
 {
diff --git a/ecp5/config.cc b/ecp5/config.cc
index 826c16a9..2d4f8b1e 100644
--- a/ecp5/config.cc
+++ b/ecp5/config.cc
@@ -274,6 +274,15 @@ std::ostream &operator<<(std::ostream &out, const ChipConfig &cc)
             out << std::endl;
         }
     }
+    for (const auto &tg : cc.tilegroups) {
+        out << ".tile_group";
+        for (const auto &tile : tg.tiles) {
+            out << " " << tile;
+        }
+        out << std::endl;
+        out << tg.config;
+        out << std::endl;
+    }
     return out;
 }
 
@@ -294,6 +303,19 @@ std::istream &operator>>(std::istream &in, ChipConfig &cc)
             TileConfig tc;
             in >> tc;
             cc.tiles[tilename] = tc;
+        } else if (verb == ".tile_group") {
+            TileGroup tg;
+            std::string line;
+            getline(in, line);
+            std::stringstream ss2(line);
+
+            std::string tile;
+            while (ss2) {
+                ss2 >> tile;
+                tg.tiles.push_back(tile);
+            }
+            in >> tg.config;
+            cc.tilegroups.push_back(tg);
         } else {
             log_error("unrecognised config entry %s\n", verb.c_str());
         }
diff --git a/ecp5/config.h b/ecp5/config.h
index 3d2ef971..c7e2c3d9 100644
--- a/ecp5/config.h
+++ b/ecp5/config.h
@@ -98,6 +98,14 @@ std::ostream &operator<<(std::ostream &out, const TileConfig &tc);
 
 std::istream &operator>>(std::istream &in, TileConfig &ce);
 
+// A group of tiles to configure at once for a particular feature that is split across tiles
+// TileGroups are currently for non-routing configuration only
+struct TileGroup
+{
+    std::vector<std::string> tiles;
+    TileConfig config;
+};
+
 // This represents the configuration of a chip at a high level
 class ChipConfig
 {
@@ -105,6 +113,7 @@ class ChipConfig
     std::string chip_name;
     std::vector<std::string> metadata;
     std::map<std::string, TileConfig> tiles;
+    std::vector<TileGroup> tilegroups;
 };
 
 std::ostream &operator<<(std::ostream &out, const ChipConfig &cc);