Add some utility methods for site instance access.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

3 files changed, 42 insertions, 13 deletions

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index cce93844..71ba46e4 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -147,7 +147,7 @@ Arch::Arch(ArchArgs args) : args(args)
 
     for (BelId bel : getBels()) {
         auto &bel_data = bel_info(chip_info, bel);
-        const SiteInstInfoPOD &site = chip_info->sites[chip_info->tiles[bel.tile].sites[bel_data.site]];
+        const SiteInstInfoPOD &site = get_site_inst(bel);
         auto iter = site_bel_pads.find(SiteBelPair(site.site_name.get(), IdString(bel_data.name)));
         if (iter != site_bel_pads.end()) {
             pads.emplace(bel);
@@ -508,7 +508,7 @@ IdStringList Arch::getPipName(PipId pip) const
     auto &pip_info = tile_type.pip_data[pip.index];
     if (pip_info.site != -1) {
         // This is either a site pin or a site pip.
-        auto &site = chip_info->sites[tile.sites[pip_info.site]];
+        auto &site = get_site_inst(pip);
         auto &bel = tile_type.bel_data[pip_info.bel];
         IdString bel_name(bel.name);
         if (bel.category == BEL_CATEGORY_LOGIC) {
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 1daf5526..fb9a36b9 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -253,6 +253,11 @@ inline const PipInfoPOD &pip_info(const ChipInfoPOD *chip_info, PipId pip)
     return loc_info(chip_info, pip).pip_data[pip.index];
 }
 
+inline const SiteInstInfoPOD &site_inst_info(const ChipInfoPOD *chip_info, int32_t tile, int32_t site)
+{
+    return chip_info->sites[chip_info->tiles[tile].sites[site]];
+}
+
 struct BelIterator
 {
     const ChipInfoPOD *chip;
@@ -832,9 +837,7 @@ struct Arch : ArchAPI<ArchRanges>
     IdStringList getBelName(BelId bel) const override
     {
         NPNR_ASSERT(bel != BelId());
-        int site_index = bel_info(chip_info, bel).site;
-        NPNR_ASSERT(site_index >= 0);
-        const SiteInstInfoPOD &site = chip_info->sites[chip_info->tiles[bel.tile].sites[site_index]];
+        const SiteInstInfoPOD &site = get_site_inst(bel);
         std::array<IdString, 2> ids{id(site.name.get()), IdString(bel_info(chip_info, bel).name)};
         return IdStringList(ids);
     }
@@ -1055,8 +1058,7 @@ struct Arch : ArchAPI<ArchRanges>
         if (wire.tile != -1) {
             const auto &tile_type = loc_info(chip_info, wire);
             if (tile_type.wire_data[wire.index].site != -1) {
-                int site_index = tile_type.wire_data[wire.index].site;
-                const SiteInstInfoPOD &site = chip_info->sites[chip_info->tiles[wire.tile].sites[site_index]];
+                const SiteInstInfoPOD &site = get_site_inst(wire);
                 std::array<IdString, 2> ids{id(site.name.get()), IdString(tile_type.wire_data[wire.index].name)};
                 return IdStringList(ids);
             }
@@ -1620,6 +1622,36 @@ struct Arch : ArchAPI<ArchRanges>
 
         return range;
     }
+
+    const char *get_site_name(int32_t tile, size_t site) const
+    {
+        return site_inst_info(chip_info, tile, site).name.get();
+    }
+
+    const char *get_site_name(BelId bel) const
+    {
+        auto &bel_data = bel_info(chip_info, bel);
+        return get_site_name(bel.tile, bel_data.site);
+    }
+
+    const SiteInstInfoPOD &get_site_inst(BelId bel) const
+    {
+        auto &bel_data = bel_info(chip_info, bel);
+        return site_inst_info(chip_info, bel.tile, bel_data.site);
+    }
+
+    const SiteInstInfoPOD &get_site_inst(WireId wire) const
+    {
+        auto &wire_data = wire_info(wire);
+        NPNR_ASSERT(wire_data.site != -1);
+        return site_inst_info(chip_info, wire.tile, wire_data.site);
+    }
+
+    const SiteInstInfoPOD &get_site_inst(PipId pip) const
+    {
+        auto &pip_data = pip_info(chip_info, pip);
+        return site_inst_info(chip_info, pip.tile, pip_data.site);
+    }
 };
 
 NEXTPNR_NAMESPACE_END
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
index e643311d..917885bd 100644
--- a/fpga_interchange/site_router.cc
+++ b/fpga_interchange/site_router.cc
@@ -691,8 +691,7 @@ bool Arch::SiteRouter::checkSiteRouting(const Context *ctx, const Arch::TileStat
     auto tile = (*iter)->bel.tile;
 
     if (verbose_site_router(ctx)) {
-        log_info("Checking site routing for site %s\n",
-                 ctx->chip_info->sites[ctx->chip_info->tiles[tile].sites[site]].name.get());
+        log_info("Checking site routing for site %s\n", ctx->get_site_name(tile, site));
     }
 
     for (CellInfo *cell : cells_in_site) {
@@ -739,11 +738,9 @@ bool Arch::SiteRouter::checkSiteRouting(const Context *ctx, const Arch::TileStat
         if (site_ok) {
             site_info.remove_routed_sources();
             NPNR_ASSERT(site_info.is_fully_routed());
-            log_info("Site %s is routable\n",
-                     ctx->chip_info->sites[ctx->chip_info->tiles[tile].sites[site]].name.get());
+            log_info("Site %s is routable\n", ctx->get_site_name(tile, site));
         } else {
-            log_info("Site %s is not routable\n",
-                     ctx->chip_info->sites[ctx->chip_info->tiles[tile].sites[site]].name.get());
+            log_info("Site %s is not routable\n", ctx->get_site_name(tile, site));
         }
     }