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| author | David Shah <davey1576@gmail.com> | 2018-10-01 17:51:36 +0100 |
|---|---|---|
| committer | David Shah <davey1576@gmail.com> | 2018-10-01 17:51:36 +0100 |
| commit | 3dfc5b864a66ba1bfc286de884bd46a859e4306d (patch) | |
| tree | 417b1d5fa0edc1423be0250c1288167ef1dc5f3c | |
| parent | c8a9bb807c21db935985a6be0d7f7deb1afd16d0 (diff) | |
| download | nextpnr-3dfc5b864a66ba1bfc286de884bd46a859e4306d.tar.gz nextpnr-3dfc5b864a66ba1bfc286de884bd46a859e4306d.tar.bz2 nextpnr-3dfc5b864a66ba1bfc286de884bd46a859e4306d.zip | |
ecp5: Remove broken DRAM timing arc
Signed-off-by: David Shah <davey1576@gmail.com>
| -rw-r--r-- | ecp5/arch.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc index 830dfc7c..6cd83cce 100644 --- a/ecp5/arch.cc +++ b/ecp5/arch.cc @@ -511,12 +511,12 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort delay.delay = 193; return true; } - +#if 0 //FIXME if (fromPort == id_WCK && (toPort == id_F0 || toPort == id_F1)) { delay.delay = 717; return true; } - +#endif if ((fromPort == id_A0 && toPort == id_WADO3) || (fromPort == id_A1 && toPort == id_WDO1) || (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) || (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) || |