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authorgatecat <gatecat@ds0.me>2022-03-17 19:24:05 +0000
committergatecat <gatecat@ds0.me>2022-03-17 19:24:05 +0000
commit14d53dfec8dba93996f5c2877d60f6ed167d14fb (patch)
treef49f9dbf30d2fb467018ec92f94eb6288169724b
parent2635bab2f1b1a32b2505e0918caa2a91c18ce571 (diff)
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clangformat
Signed-off-by: gatecat <gatecat@ds0.me>
-rw-r--r--ice40/pack.cc3
-rw-r--r--nexus/arch.cc2
-rw-r--r--nexus/pack.cc4
3 files changed, 5 insertions, 4 deletions
diff --git a/ice40/pack.cc b/ice40/pack.cc
index f533941d..2b5def46 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -59,7 +59,8 @@ static void pack_lut_lutffs(Context *ctx)
if (ctx->verbose)
log_info("found attached dff %s\n", dff->name.c_str(ctx));
auto dff_bel = dff->attrs.find(id_BEL);
- if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() && lut_bel->second != dff_bel->second) {
+ if (lut_bel != ci->attrs.end() && dff_bel != dff->attrs.end() &&
+ lut_bel->second != dff_bel->second) {
// Locations don't match, can't pack
} else {
lut_to_lc(ctx, ci, packed.get(), false);
diff --git a/nexus/arch.cc b/nexus/arch.cc
index 39e51a5b..9679c3fb 100644
--- a/nexus/arch.cc
+++ b/nexus/arch.cc
@@ -486,7 +486,7 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
if (fromPort == id_CLK)
return false; // don't include delays that are actually clock-to-out here
return lookup_cell_delay(cell->tmg_index, lookup_port(fromPort), lookup_port(toPort), delay);
- } else if(cell->type == id_DCS) {
+ } else if (cell->type == id_DCS) {
if (fromPort == id_SELFORCE || fromPort == id_SEL) {
return false;
}
diff --git a/nexus/pack.cc b/nexus/pack.cc
index bb62ec85..26da3dc5 100644
--- a/nexus/pack.cc
+++ b/nexus/pack.cc
@@ -2007,14 +2007,14 @@ struct NexusPacker
copy_constraint(ci, id_CLK0, id_DCSOUT);
} else if (!have_clk0 && have_clk1) {
copy_constraint(ci, id_CLK1, id_DCSOUT);
- } else if ( have_clk0 && have_clk1) {
+ } else if (have_clk0 && have_clk1) {
set_period(ci, id_DCSOUT, std::min(period_clk0, period_clk1));
}
} else if (ci->type == id_OSC_CORE) {
int div = int_or_default(ci->params, id_HF_CLK_DIV, 128);
const float tol = 1.07f; // OSCA has +/-7% frequency tolerance, assume the worst case.
set_period(ci, id_HFCLKOUT, delay_t((1.0e6 / 450) * (div + 1) / tol));
- set_period(ci, id_LFCLKOUT, delay_t((1.0e9 / 32) / tol));
+ set_period(ci, id_LFCLKOUT, delay_t((1.0e9 / 32) / tol));
} else if (ci->type == id_PLL_CORE) {
static const std::array<IdString, 6> div{id_DIVA, id_DIVB, id_DIVC, id_DIVD, id_DIVE, id_DIVF};
static const std::array<IdString, 6> output{id_CLKOP, id_CLKOS, id_CLKOS2,