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module pll_12_25(
input clk12m_in,
output clk12m_out,
output clk25m_out,
input reset,
output lock
);
`ifndef verilator
// generated by icecube2 wizard
SB_PLL40_2_PAD pll_inst(.PACKAGEPIN(clk12m_in),
.PLLOUTCOREA(),
.PLLOUTCOREB(),
.PLLOUTGLOBALA(clk12m_out),
.PLLOUTGLOBALB(clk25m_out),
.EXTFEEDBACK(),
.DYNAMICDELAY(),
.RESETB(reset),
.BYPASS(1'b0),
.LATCHINPUTVALUE(),
.LOCK(lock),
.SDI(),
.SDO(),
.SCLK());
//\\ Fin=12, Fout=25;
defparam pll_inst.DIVR = 4'b0000;
defparam pll_inst.DIVF = 7'b1000010;
defparam pll_inst.DIVQ = 3'b101;
defparam pll_inst.FILTER_RANGE = 3'b001;
defparam pll_inst.FEEDBACK_PATH = "SIMPLE";
defparam pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
defparam pll_inst.FDA_FEEDBACK = 4'b0000;
defparam pll_inst.SHIFTREG_DIV_MODE = 2'b00;
defparam pll_inst.PLLOUT_SELECT_PORTB = "GENCLK";
defparam pll_inst.ENABLE_ICEGATE_PORTA = 1'b0;
defparam pll_inst.ENABLE_ICEGATE_PORTB = 1'b0;
`endif
endmodule
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