1 files changed, 33 insertions, 0 deletions
diff --git a/ice40/regressions/issue0065/ice40_pll_12_216.v b/ice40/regressions/issue0065/ice40_pll_12_216.v
new file mode 100644
index 0000000..c778e5c
--- /dev/null
+++ b/ice40/regressions/issue0065/ice40_pll_12_216.v
@@ -0,0 +1,33 @@
+/**
+ * PLL configuration
+ *
+ * This Verilog module was generated automatically
+ * using the icepll tool from the IceStorm project.
+ * Use at your own risk.
+ *
+ * Given input frequency:        12.000 MHz
+ * Requested output frequency:  216.000 MHz
+ * Achieved output frequency:   216.000 MHz
+ */
+
+module ice40_pll_12_216(
+	input  clock_in,
+	output clock_out,
+	output locked
+	);
+
+SB_PLL40_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'b0000),		// DIVR =  0
+		.DIVF(7'b1000111),	// DIVF = 71
+		.DIVQ(3'b010),		// DIVQ =  2
+		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
+	) uut (
+		.LOCK(locked),
+		.RESETB(1'b1),
+		.BYPASS(1'b0),
+		.REFERENCECLK(clock_in),
+		.PLLOUTCORE(clock_out)
+		);
+
+endmodule