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<!DOCTYPE html>
<html><head><meta charset="UTF-8">
<style>
.ctab {
margin-left: auto;
margin-right: auto;
border: 1px solid gray;
}
.ctab td, .ctab th {
padding: 3px;
border: 1px solid gray;
}
</style>
<title>Project IceStorm</title>
</head><body>
<h1>Project IceStorm</h1>
<p>
<b>2017-03-13:</b> Released support for LP384 chips (in all package variants).<br/>
<b>2016-02-07:</b> Support for all package variants of LP1K, LP4K, LP8K and HX1K, HX4K, and HX8K.<br/>
<b>2016-01-17:</b> First release of IceTime timing analysis. Video: <a href="https://youtu.be/IG5CpFJRnOk">https://youtu.be/IG5CpFJRnOk</a><br/>
<b>2015-12-27:</b> <a href="http://www.clifford.at/papers/2015/icestorm-flow/">Presentation</a> of the IceStorm flow at 32C3 (<a href="https://www.youtube.com/watch?v=SOn0g3k0FlE">Video on Youtube</a>).<br/>
<b>2015-07-19:</b> Released support for 8k chips. Moved IceStorm source code to GitHub.<br/>
<b>2015-05-27:</b> We have a working fully Open Source flow with <a href="http://www.clifford.at/yosys/">Yosys</a> and <a href="https://github.com/cseed/arachne-pnr">Arachne-pnr</a>! Video: <a href="http://youtu.be/yUiNlmvVOq8">http://youtu.be/yUiNlmvVOq8</a><br/>
<b>2015-04-13:</b> Complete rewrite of IceUnpack, added IcePack, some major documentation updates<br/>
<b>2015-03-22:</b> First public release and short YouTube video demonstrating our work: <a href="http://youtu.be/u1ZHcSNDQMM">http://youtu.be/u1ZHcSNDQMM</a>
</p>
<h2>What is Project IceStorm?</h2>
<p>
Project IceStorm aims at reverse engineering and documenting the bitstream
format of Lattice iCE40 FPGAs and providing simple tools for analyzing and
creating bitstream files. The IceStorm flow (<a
href="http://www.clifford.at/yosys/">Yosys</a>, <a
href="https://github.com/cseed/arachne-pnr">Arachne-pnr</a>, and IceStorm) is a
fully open source Verilog-to-Bitstream flow for iCE40 FPGAs.
</p>
<p>
The focus of the project is on the iCE40 LP/HX 1K/4K/8K chips. (Most of the
work was done on HX1K-TQ144 and HX8K-CT256 parts.)
</p>
<h2>Why the Lattice iCE40?</h2>
<p>
It has a very minimalistic architecture with a very regular structure. There are not many
different kinds of tiles or special function units. This makes it both ideal for
reverse engineering and as a reference platform for general purpose FPGA tool development.
</p>
<p>
Also, with the <a href="http://www.latticesemi.com/icestick">Lattice iCEstick</a> there is
a cheap and easy to use development platform available, which makes the part interesting
for all kinds of projects. (The iCEstick features an HX1K device. Lattice also sells an <a
href="http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx">iCE40-HX8K
Breakout Board</a> featuring an HX8K chip.)
</p>
<h2>What is the Status of the Project?</h2>
<p>
We are pretty confident that we have the 1K and 8K devices completely reverse
engineered. For example, it seems we can create correct functional Verilog
models for all bitstreams generated by Lattice iCEcube2 for the iCE40
HX1K-TQ144 and the iCE40 HX8K-CT256 using our <tt>icebox_vlog</tt> tool.
</p>
<p id="flags">
Here is a list of currently supported parts and the corresponding options for arachne-pnr (place and route) and icetime (timing analysis):
</p>
<table class="ctab">
<tr><th>Part</th><th>Package</th><th>Pin Spacing</th><th>I/Os</th><th>arachne-pnr opts</th><th>icetime opts</th></tr>
<tr><td>iCE40-LP1K-SWG16TR</td><td>16-ball WLCSP (1.40 x 1.48 mm)</td><td>0.35 mm</td><td>10</td><td>-d 1k -P swg16tr</td><td>-d lp1k</td></tr>
<tr><td>iCE40-LP384-CM36</td><td>36-ball ucBGA (2.5 x 2.5 mm)</td><td>0.40 mm</td><td>25</td><td>-d 384 -P cm36</td><td>-d lp384</td></tr>
<tr><td>iCE40-LP1K-CM36</td><td>36-ball ucBGA (2.5 x 2.5 mm)</td><td>0.40 mm</td><td>25</td><td>-d 1k -P cm36</td><td>-d lp1k</td></tr>
<tr><td>iCE40-LP384-CM49</td><td>49-ball ucBGA (3 x 3 mm)</td><td>0.40 mm</td><td>37</td><td>-d 384 -P cm49</td><td>-d lp384</td></tr>
<tr><td>iCE40-LP1K-CM49</td><td>49-ball ucBGA (3 x 3 mm)</td><td>0.40 mm</td><td>35</td><td>-d 1k -P cm49</td><td>-d lp1k</td></tr>
<tr><td>iCE40-LP1K-CM81</td><td>81-ball ucBGA (4 x 4 mm)</td><td>0.40 mm</td><td>63</td><td>-d 1k -P cm81</td><td>-d lp1k</td></tr>
<tr><td>iCE40-LP4K-CM81</td><td>81-ball ucBGA (4 x 4 mm)</td><td>0.40 mm</td><td>63</td><td>-d 8k -P cm81:4k</td><td>-d lp8k</td></tr>
<tr><td>iCE40-LP8K-CM81</td><td>81-ball ucBGA (4 x 4 mm)</td><td>0.40 mm</td><td>63</td><td>-d 8k -P cm81</td><td>-d lp8k</td></tr>
<tr><td>iCE40-LP1K-CM121</td><td>121-ball ucBGA (5 x 5 mm)</td><td>0.40 mm</td><td>95</td><td>-d 1k -P cm121</td><td>-d lp1k</td></tr>
<tr><td>iCE40-LP4K-CM121</td><td>121-ball ucBGA (5 x 5 mm)</td><td>0.40 mm</td><td>93</td><td>-d 8k -P cm121:4k</td><td>-d lp8k</td></tr>
<tr><td>iCE40-LP8K-CM121</td><td>121-ball ucBGA (5 x 5 mm)</td><td>0.40 mm</td><td>93</td><td>-d 8k -P cm121</td><td>-d lp8k</td></tr>
<tr><td>iCE40-LP4K-CM225</td><td>225-ball ucBGA (7 x 7 mm)</td><td>0.40 mm</td><td>167</td><td>-d 8k -P cm225:4k</td><td>-d lp8k</td></tr>
<tr><td>iCE40-LP8K-CM225</td><td>225-ball ucBGA (7 x 7 mm)</td><td>0.40 mm</td><td>178</td><td>-d 8k -P cm225</td><td>-d lp8k</td></tr>
<tr><td>iCE40-HX8K-CM225</td><td>225-ball ucBGA (7 x 7 mm)</td><td>0.40 mm</td><td>178</td><td>-d 8k -P cm225</td><td>-d hx8k</td></tr>
<tr><td>iCE40-LP384-QN32</td><td>32-pin QFN (5 x 5 mm)</td><td>0.50 mm</td><td>21</td><td>-d 384 -P qn32</td><td>-d lp384</td></tr>
<tr><td>iCE40-LP1K-QN84</td><td>84-pin QFNS (7 x 7 mm)</td><td>0.50 mm</td><td>67</td><td>-d 1k -P qn84</td><td>-d lp1k</td></tr>
<tr><td>iCE40-LP1K-CB81</td><td>81-ball csBGA (5 x 5 mm)</td><td>0.50 mm</td><td>62</td><td>-d 1k -P cb81</td><td>-d lp1k</td></tr>
<tr><td>iCE40-LP1K-CB121</td><td>121-ball csBGA (6 x 6 mm)</td><td>0.50 mm</td><td>92</td><td>-d 1k -P cb121</td><td>-d lp1k</td></tr>
<tr><td>iCE40-HX1K-CB132</td><td>132-ball csBGA (8 x 8 mm)</td><td>0.50 mm</td><td>95</td><td>-d 1k -P cb132</td><td>-d hx1k</td></tr>
<tr><td>iCE40-HX4K-CB132</td><td>132-ball csBGA (8 x 8 mm)</td><td>0.50 mm</td><td>95</td><td>-d 8k -P cb132:4k</td><td>-d hx8k</td></tr>
<tr><td>iCE40-HX8K-CB132</td><td>132-ball csBGA (8 x 8 mm)</td><td>0.50 mm</td><td>95</td><td>-d 8k -P cb132</td><td>-d hx8k</td></tr>
<tr><td>iCE40-HX1K-VQ100</td><td>100-pin VQFP (14 x 14 mm)</td><td>0.50 mm</td><td>72</td><td>-d 1k -P vq100</td><td>-d hx1k</td></tr>
<tr><td>iCE40-HX1K-TQ144</td><td>144-pin TQFP (20 x 20 mm)</td><td>0.50 mm</td><td>96</td><td>-d 1k -P tq144</td><td>-d hx1k</td></tr>
<tr><td>iCE40-HX4K-TQ144</td><td>144-pin TQFP (20 x 20 mm)</td><td>0.50 mm</td><td>107</td><td>-d 8k -P tq144:4k</td><td>-d hx8k</td></tr>
<tr><td>iCE40-HX8K-CT256</td><td>256-ball caBGA (14 x 14 mm)</td><td>0.80 mm</td><td>206</td><td>-d 8k -P ct256</td><td>-d hx8k</td></tr>
</table>
<p>
Current work focuses on further improving our timing analysis flow.
</p>
<h2>How do I use the Fully Open Source iCE40 Flow?</h2>
<p>
Synthesis for iCE40 FPGAs can be done with <a href="http://www.clifford.at/yosys/">Yosys</a>.
Place-and-route can be done with <a href="https://github.com/cseed/arachne-pnr">arachne-pnr</a>.
Here is an example script for implementing and programming the <a
href="https://github.com/cseed/arachne-pnr/tree/master/examples/rot">rot example from
arachne-pnr</a> (this example targets the iCEstick development board):
</p>
<pre style="padding-left: 3em">yosys -p "synth_ice40 -blif rot.blif" rot.v
arachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc
icepack rot.asc rot.bin
iceprog rot.bin</pre>
<p>
A simple timing analysis report can be generated using the <tt>icetime</tt> utility:
</p>
<pre style="padding-left: 3em">icetime -tmd hx1k rot.asc</pre>
<h2 id="install">Where are the Tools? How to install?</h2>
<p>
Installing prerequisites (this command is for Ubuntu 14.04):
</p>
<pre style="padding-left: 3em">
sudo apt-get install build-essential clang bison flex libreadline-dev \
gawk tcl-dev libffi-dev git mercurial graphviz \
xdot pkg-config python python3 libftdi-dev
</pre>
<p>
On Fedora 24 the following command installs all prerequisites:
</p>
<pre style="padding-left: 3em">
sudo dnf install make automake gcc gcc-c++ kernel-devel clang bison \
flex readline-devel gawk tcl-devel libffi-devel git mercurial \
graphviz python-xdot pkgconfig python python3 libftdi-devel
</pre>
<p>
Installing the <a href="https://github.com/cliffordwolf/icestorm">IceStorm Tools</a> (icepack, icebox, iceprog, icetime, chip databases):
</p>
<pre style="padding-left: 3em">git clone https://github.com/cliffordwolf/icestorm.git icestorm
cd icestorm
make -j$(nproc)
sudo make install</pre>
<p>
Installing <a href="https://github.com/cseed/arachne-pnr">Arachne-PNR</a> (the place&route tool):
</p>
<pre style="padding-left: 3em">git clone https://github.com/cseed/arachne-pnr.git arachne-pnr
cd arachne-pnr
make -j$(nproc)
sudo make install</pre>
<p>
Installing <a href="http://www.clifford.at/yosys/">Yosys</a> (Verilog synthesis):
</p>
<pre style="padding-left: 3em">git clone https://github.com/cliffordwolf/yosys.git yosys
cd yosys
make -j$(nproc)
sudo make install</pre>
<p>
The Arachne-PNR build converts the IceStorm text chip databases into the arachne-pnr binary chip databases. Always rebuild Arachne-PNR
after updating your IceStorm installation.
</p>
<p>
<b>Notes for Linux:</b> Create a file <tt>/etc/udev/rules.d/53-lattice-ftdi.rules</tt> with the following line in it to allow uploading
bit-streams to a Lattice iCEstick and/or a Lattice iCE40-HX8K Breakout Board as unprivileged user:
</p>
<pre style="padding-left: 3em">ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="0660", GROUP="plugdev", TAG+="uaccess"</pre>
<p>
<b>Notes for Archlinux:</b> just install <a href="https://aur.archlinux.org/packages/icestorm-git/">icestorm-git</a>, <a href="https://aur.archlinux.org/packages/arachne-pnr-git/">arachne-pnr-git</a> and <a href="https://aur.archlinux.org/packages/yosys-git/">yosys-git</a> from the Arch User Repository (no need to follow the install instructions above).
</p>
<p>
<b>Notes for OSX:</b> Please follow the <a href="notes_osx.html">additional instructions for OSX</a> to install on OSX.
</p>
<p>
Please <a href="https://github.com/cliffordwolf/icestorm/issues/new">file an issue on github</a> if you have additional notes to
share regarding the install procedures on the operating system of your choice.
</p>
<h2>What are the IceStorm Tools?</h2>
<p>
The IceStorm Tools are a couple of small programs for working with iCE40 bitstream files and our
ASCII representation of it. The complete Open Source iCE40 Flow consists of the <a
href="https://github.com/cliffordwolf/icestorm">IceStorm Tools</a>, <a
href="https://github.com/cseed/arachne-pnr">Arachne-PNR</a>, and <a
href="http://www.clifford.at/yosys/">Yosys</a>.
</p>
<h3>IcePack/IceUnpack</h3>
<p>
The <span style="font-family:monospace">iceunpack</span> program converts an iCE40 <span style="font-family:monospace">.bin</span> file into the IceStorm ASCII format
that has blocks of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> for the config bits for each tile in the chip. The
<span style="font-family:monospace">icepack</span> program converts such an ASCII file back to an iCE40 <span style="font-family:monospace">.bin</span> file. All
other IceStorm Tools operate on the ASCII file format, not the bitstream binaries.
</p>
<h3>IceTime</h3>
<p>
The <span style="font-family:monospace">icetime</span> program is an iCE40 timing analysis tool. It reads designs in IceStorm ASCII format and writes times timing
netlists that can be used in external timing analysers. It also includes a simple topological timing analyser that can be used to create timing reports.
</p>
<h3>IceBox</h3>
<p>
A python library and various tools for working with IceStorm ASCII files and accessing
the device database. For example <span style="font-family:monospace">icebox_vlog</span> converts our ASCII file
dump of a bitstream into a Verilog file that implements an equivalent circuit.
</p>
<h3>IceProg</h3>
<p>
A small driver program for the FTDI-based programmer used on the iCEstick and HX8K development boards.
</p>
<h3>IceMulti</h3>
<p>
A tool for packing multiple bitstream files into one iCE40 multiboot image file.
</p>
<h3>IcePLL</h3>
<p>
A small program for calculating iCE40 PLL configuration parameters.
</p>
<h3>IceBRAM</h3>
<p>
A small program for swapping the BRAM contents in IceStorm ASCII files. E.g.
for changing the firmware image in a SoC design without re-running synthesis
and place&route.
</p>
<h3>ChipDB</h3>
<p>
The IceStorm Makefile builds and installs two files: <span style="font-family:monospace">chipdb-1k.txt</span> and <span style="font-family:monospace">chipdb-8k.txt</span>.
This files contain all the relevant information for arachne-pnr to place&route a design and
create an IceStorm ASCII file for the placed and routed design.
</p>
<p>
<i>IcePack/IceUnpack, IceBox, IceProg, IceTime, and IcePLL are written by Clifford Wolf. IcePack/IceUnpack is based on a reference implementation provided by Mathias Lasser. IceMulti is written by Marcus Comstedt.</i>
</p>
<h2>Where do I get support or meet other IceStorm users?</h2>
<p>
If you have a question regarding the IceStorm flow, use the <a href="http://stackoverflow.com/questions/tagged/yosys">yosys tag on stackoverflow</a>
to ask your question. If your question is a general question about Verilog HDL design, please consider using the
<a href="http://stackoverflow.com/questions/tagged/verilog">verilog tag on stackoverflow</a> instead.
</p>
<p>
For general discussions go to the <a href="https://www.reddit.com/r/yosys/">Yosys Subreddit</a> or <a href="http://webchat.freenode.net/?channels=yosys">#yosys on freenode IRC</a>.
</p>
<p>
If you have a bug report please file an issue on github. (<a href="https://github.com/cliffordwolf/icestorm/issues">IceStorm Issue Tracker</a>,
<a href="https://github.com/cliffordwolf/yosys/issues">Yosys Issue Tracker</a>, <a href="https://github.com/cseed/arachne-pnr/issues">Arachne-PNR Issue Tracker</a>)
</p>
<h2 id="docs">Where is the Documentation?</h2>
<p>
Recommended reading:
<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/iCE/iCE40LPHXFamilyDataSheet.pdf">Lattice iCE40 LP/HX Family Datasheet</a>,
<a href="http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201504.pdf">Lattice iCE Technology Library</a>
(Especially the three pages on "Architecture Overview", "PLB Blocks", "Routing", and "Clock/Control Distribution Network" in
the Lattice iCE40 LP/HX Family Datasheet. Read that first, then come back here.)
</p>
<p>
The FPGA fabric is divided into tiles. There are IO, RAM and LOGIC tiles.
</p>
<ul>
<li><a href="logic_tile.html">LOGIC Tile Documentation</a></li>
<li><a href="io_tile.html">IO Tile Documentation</a></li>
<li><a href="ram_tile.html">RAM Tile Documentation</a></li>
<li><a href="format.html">The Bitstream File Format</a></li>
<li><a href="bitdocs-1k/">The iCE40 HX1K Bit Docs</a></li>
<li><a href="bitdocs-8k/">The iCE40 HX8K Bit Docs</a></li>
</ul>
<p>
The <span style="font-family:monospace">iceunpack</span> program can be used to convert the bitstream into an ASCII file
that has a block of <span style="font-family:monospace">0</span> and <span style="font-family:monospace">1</span> characters for each tile. For example:
</p>
<pre style="padding-left: 3em">.logic_tile 12 12
000000000000000000000000000000000000000000000000000000
000000000000000000000011010000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000001011000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000
000000000000000000000000001000001000010101010000000000
000000000000000000000000000101010000101010100000000000</pre>
<p>
This bits are referred to as <span style="font-family:monospace">B<i>y</i>[<i>x</i>]</span> in the documentation. For example, <span style="font-family:monospace">B0</span> is the first
line, <span style="font-family:monospace">B0[0]</span> the first bit in the first line, and <span style="font-family:monospace">B15[53]</span> the last bit in the last line.
</p>
<p>
The <span style="font-family:monospace">icebox_explain</span> program can be used to turn this block of config bits into a description of the cell
configuration:
</p>
<pre style="padding-left: 3em">.logic_tile 12 12
LC_7 0101010110101010 0000
buffer local_g0_2 lutff_7/in_3
buffer local_g1_4 lutff_7/in_0
buffer sp12_h_r_18 local_g0_2
buffer sp12_h_r_20 local_g1_4</pre>
<p>
IceBox contains a database of the wires and configuration bits that can be found in iCE40 tiles. This database can be accessed
via the IceBox Python API. But IceBox is a large hack. So it is recommended to only use the IceBox API
to export this database into a format that fits the target application. See <span style="font-family:monospace">icebox_chipdb</span> for
an example program that does that.
</p>
<p>
The recommended approach for learning how to use this documentation is to
synthesize very simple circuits using Yosys and Arachne-pnr, run the icestorm
tool <span style="font-family:monospace">icebox_explain</span> on the resulting bitstream files, and analyze the
results using the HTML export of the database mentioned above.
<span style="font-family:monospace">icebox_vlog</span> can be used to convert the bitstream to Verilog. The
output file of this tool will also outline the signal paths in comments added
to the generated Verilog code.
</p>
<p>
For example, consider the following Verilog and PCF files:
</p>
<pre style="padding-left: 3em">// example.v
module top (input a, b, output y);
assign y = a & b;
endmodule
# example.pcf
set_io a 1
set_io b 10
set_io y 11</pre>
<p>
And run them through Yosys, Arachne-PNR and IcePack:
</p>
<pre style="padding-left: 3em">$ yosys -p 'synth_ice40 -top top -blif example.blif' example.v
$ arachne-pnr -d 1k -o example.asc -p example.pcf example.blif
$ icepack example.asc example.bin
</pre>
<p>
We would get something like the following <span style="font-family:monospace">icebox_explain</span> output:
</p>
<pre style="padding-left: 3em">$ icebox_explain example.asc
Reading file 'example.asc'..
Fabric size (without IO tiles): 12 x 16
.io_tile 0 10
IOB_1 PINTYPE_0
IOB_1 PINTYPE_3
IOB_1 PINTYPE_4
IoCtrl IE_0
IoCtrl IE_1
IoCtrl REN_0
buffer local_g0_5 io_1/D_OUT_0
buffer logic_op_tnr_5 local_g0_5
.io_tile 0 14
IOB_1 PINTYPE_0
IoCtrl IE_1
IoCtrl REN_0
buffer io_1/D_IN_0 span4_vert_b_6
.io_tile 0 11
IOB_0 PINTYPE_0
IoCtrl IE_0
IoCtrl REN_1
routing span4_vert_t_14 span4_horz_13
.logic_tile 1 11
LC_5 0001000000000000 0000
buffer local_g0_0 lutff_5/in_1
buffer local_g3_0 lutff_5/in_0
buffer neigh_op_lft_0 local_g0_0
buffer sp4_h_r_24 local_g3_0</pre>
<p>
And something like the following <span style="font-family:monospace">icebox_vlog</span> output:
</p>
<pre style="padding-left: 3em">$ icebox_vlog -p example.pcf example.asc
// Reading file 'example.asc'..
module chip (output y, input b, input a);
wire y;
// io_0_10_1
// (0, 10, 'io_1/D_OUT_0')
// (0, 10, 'io_1/PAD')
// (0, 10, 'local_g0_5')
// (0, 10, 'logic_op_tnr_5')
// (0, 11, 'logic_op_rgt_5')
// (0, 12, 'logic_op_bnr_5')
// (1, 10, 'neigh_op_top_5')
// (1, 11, 'lutff_5/out')
// (1, 12, 'neigh_op_bot_5')
// (2, 10, 'neigh_op_tnl_5')
// (2, 11, 'neigh_op_lft_5')
// (2, 12, 'neigh_op_bnl_5')
wire b;
// io_0_11_0
// (0, 11, 'io_0/D_IN_0')
// (0, 11, 'io_0/PAD')
// (1, 10, 'neigh_op_tnl_0')
// (1, 10, 'neigh_op_tnl_4')
// (1, 11, 'local_g0_0')
// (1, 11, 'lutff_5/in_1')
// (1, 11, 'neigh_op_lft_0')
// (1, 11, 'neigh_op_lft_4')
// (1, 12, 'neigh_op_bnl_0')
// (1, 12, 'neigh_op_bnl_4')
wire a;
// io_0_14_1
// (0, 11, 'span4_horz_13')
// (0, 11, 'span4_vert_t_14')
// (0, 12, 'span4_vert_b_14')
// (0, 13, 'span4_vert_b_10')
// (0, 14, 'io_1/D_IN_0')
// (0, 14, 'io_1/PAD')
// (0, 14, 'span4_vert_b_6')
// (0, 15, 'span4_vert_b_2')
// (1, 11, 'local_g3_0')
// (1, 11, 'lutff_5/in_0')
// (1, 11, 'sp4_h_r_24')
// (1, 13, 'neigh_op_tnl_2')
// (1, 13, 'neigh_op_tnl_6')
// (1, 14, 'neigh_op_lft_2')
// (1, 14, 'neigh_op_lft_6')
// (1, 15, 'neigh_op_bnl_2')
// (1, 15, 'neigh_op_bnl_6')
// (2, 11, 'sp4_h_r_37')
// (3, 11, 'sp4_h_l_37')
assign y = /* LUT 1 11 5 */ b ? a : 0;
endmodule</pre>
<h2>Links</h2>
<p>
Links to related projects. Contact me at clifford@clifford.at if you have an interesting and relevant link.
</p>
<ul>
<li><a href="http://www.excamera.com/sphinx/article-j1a-swapforth.html">J1a SwapForth built with IceStorm</a>
<li><a href="https://github.com/davidcarne/iceBurn">Lattice iCEBlink40 Programming Tool</a>
<li><a href="https://github.com/reactive-systems/icedude">Another iCEBlink40 Programming Tool</a>
<li><a href="https://github.com/knielsen/ice40_viewer">iCE40 layout viewer</a>
<li><a href="http://drom.io/icedrom/">icedrom iCE40 netlist viewer</a>
</ul>
<h3>iCE40 Boards</h3>
<ul>
<li><a href="http://www.latticesemi.com/icestick">Lattice iCEstick</a>
<li><a href="http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx">Lattice iCE40-HX8K Breakout Board</a>
<li><a href="http://icoboard.org/">IcoBoard</a>
<li><a href="http://wiggleport.com">wiggleport</a>
<li><a href="https://hackaday.io/project/6636-iced-an-arduino-style-board-with-ice-fpga">ICEd = an Arduino Style Board, with ICE FPGA</a>
<li><a href="https://hackaday.io/project/7982-cat-board">CAT Board</a>
<li><a href="http://opencores.org/project,ecowlogic-pico">eCow-Logic pico-ITX Lattice ICE40 board</a>
<li><a href="https://www.nandland.com/blog/go-board-introduction.html">Nandland Go Board</a>
<li><a href="https://folknologylabs.wordpress.com/2016/08/17/the-lull-before-the-storm/">myStorm board (iCE40 + STM32)</a>
<li><a href="https://github.com/tvelliott/dsp_ice">DSP iCE board (another iCE40 + STM32 board)</a>
<li><a href="https://www.crowdsupply.com/qwerty-embedded-design/beaglewire">BeagleWire iCE40 FPGA BeagleBone cape</a>
</ul>
<h3>Lectures and Tutorials</h3>
<ul>
<li><a href="https://media.ccc.de/v/32c3-7139-a_free_and_open_source_verilog-to-bitstream_flow_for_ice40_fpgas">A Free and Open Source Verilog-to-Bitstream Flow for iCE40 FPGAs [32c3]</a>
<li><a href="https://www.youtube.com/watch?v=s7fNTF8nd8A">Synthesizing Verilog for Lattice ICE40 FPGAs (Paul Martin)</a>
<li><a href="https://github.com/Obijuan/open-fpga-verilog-tutorial/wiki">A Spanish FPGA Tutorial using IceStorm</a>
</ul>
<h3>Other FPGA reverse engineering projects</h3>
<ul>
<li><a href="https://github.com/Wolfgang-Spraul/fpgatools">Xilinx xc6slx9 reverse engineering, Wolfgang Spraul</a>
<li><a href="http://www.fabienm.eu/flf/wp-content/uploads/2014/11/Note2008.pdf">From the bitstream to the netlist, Jean-Baptiste Note and Éric Rannaud</a>
<li><a href="http://git.bfuser.eu/?p=marex/typhoon.git;a=commit">Cyclone IV EP4CE6 reverse engineering, Marek Vasut</a>
</ul>
<hr>
<p>
In papers and reports, please refer to Project IceStorm as follows: Clifford Wolf, Mathias Lasser. Project IceStorm. http://www.clifford.at/icestorm/,
e.g. using the following BibTeX code:
</p>
<pre>@MISC{IceStorm,
author = {Clifford Wolf and Mathias Lasser},
title = {Project IceStorm},
howpublished = "\url{http://www.clifford.at/icestorm/}"
}</pre>
<hr>
<p>
<i>Documentation mostly by Clifford Wolf <clifford@clifford.at> in 2015. Based on research by Mathias Lasser and Clifford Wolf.<br/>
Buy an <a href="http://www.latticesemi.com/icestick">iCEstick</a> or <a href="http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx">iCE40-HX8K Breakout Board</a> from Lattice and see what you can do with the tools and information provided here.</i>
</p>
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