diff options
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/icestick/.gitignore | 5 | ||||
| -rw-r--r-- | examples/icestick/Makefile | 15 | ||||
| -rw-r--r-- | examples/icestick/rs232demo.v | 8 | ||||
| -rw-r--r-- | examples/icestick/rs232demo_tb.v | 75 |
4 files changed, 103 insertions, 0 deletions
diff --git a/examples/icestick/.gitignore b/examples/icestick/.gitignore index 539898f..bb30525 100644 --- a/examples/icestick/.gitignore +++ b/examples/icestick/.gitignore @@ -6,3 +6,8 @@ rs232demo.bin rs232demo.blif rs232demo.asc rs232demo.rpt +rs232demo_tb +rs232demo_tb.vcd +rs232demo_syn.v +rs232demo_syntb +rs232demo_syntb.vcd diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile index 9294608..d687d14 100644 --- a/examples/icestick/Makefile +++ b/examples/icestick/Makefile @@ -18,6 +18,21 @@ all: $(PROJ).rpt $(PROJ).bin %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< +%_tb: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb + ./$< +vcd=$@ + +%_syn.v: %.blif + yosys -o $@ $^ + +%_syntb: %_tb.v %_syn.v + iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + +%_syntb.vcd: %_syntb + ./$< +vcd=$@ + prog: $(PROJ).bin iceprog $< diff --git a/examples/icestick/rs232demo.v b/examples/icestick/rs232demo.v index f9e7546..40347e8 100644 --- a/examples/icestick/rs232demo.v +++ b/examples/icestick/rs232demo.v @@ -19,6 +19,14 @@ module top ( reg [3:0] bit_cnt = 0; reg recv = 0; + initial begin + LED1 = 0; + LED2 = 0; + LED3 = 0; + LED4 = 0; + LED5 = 0; + end + always @(posedge clk) begin buffer_valid <= 0; if (!recv) begin diff --git a/examples/icestick/rs232demo_tb.v b/examples/icestick/rs232demo_tb.v new file mode 100644 index 0000000..3e95abf --- /dev/null +++ b/examples/icestick/rs232demo_tb.v @@ -0,0 +1,75 @@ +module testbench; + localparam integer PERIOD = 12000000 / 9600; + + reg clk = 1; + always #5 clk = ~clk; + + reg RX = 1; + wire TX; + wire LED1; + wire LED2; + wire LED3; + wire LED4; + wire LED5; + + top uut ( + .clk (clk ), + .RX (RX ), + .TX (TX ), + .LED1(LED1), + .LED2(LED2), + .LED3(LED3), + .LED4(LED4), + .LED5(LED5) + ); + + task send_byte; + input [7:0] c; + integer i; + begin + RX <= 0; + repeat (PERIOD) @(posedge clk); + + for (i = 0; i < 8; i = i+1) begin + RX <= c[i]; + repeat (PERIOD) @(posedge clk); + end + + RX <= 1; + repeat (PERIOD) @(posedge clk); + end + endtask + + reg [4095:0] vcdfile; + + initial begin + if ($value$plusargs("vcd=%s", vcdfile)) begin + $dumpfile(vcdfile); + $dumpvars(0, testbench); + end + + // send break + repeat (20 * PERIOD) @(posedge clk); + RX <= 0; + repeat (20 * PERIOD) @(posedge clk); + RX <= 1; + repeat (20 * PERIOD) @(posedge clk); + + // turn all LEDs on + send_byte("1"); + send_byte("2"); + send_byte("3"); + send_byte("4"); + send_byte("5"); + + // turn all LEDs off + send_byte("1"); + send_byte("2"); + send_byte("3"); + send_byte("4"); + send_byte("5"); + + repeat (10 * PERIOD) @(posedge clk); + $finish; + end +endmodule |