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author | Clifford Wolf <clifford@clifford.at> | 2015-10-25 15:28:58 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-10-25 15:28:58 +0100 |
commit | e4ed27a3ab81284d556be3dde77a64caab895397 (patch) | |
tree | bd0764be6e62f25e7169cacfb0f517a894acf717 /icetime/mktest.py | |
parent | 2a8c4b7e6cc60d87ff75576426dedcb9c62e64c8 (diff) | |
download | icestorm-e4ed27a3ab81284d556be3dde77a64caab895397.tar.gz icestorm-e4ed27a3ab81284d556be3dde77a64caab895397.tar.bz2 icestorm-e4ed27a3ab81284d556be3dde77a64caab895397.zip |
icetime progress
Diffstat (limited to 'icetime/mktest.py')
-rw-r--r-- | icetime/mktest.py | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/icetime/mktest.py b/icetime/mktest.py index 5d888f4..5154b02 100644 --- a/icetime/mktest.py +++ b/icetime/mktest.py @@ -17,10 +17,9 @@ with open("%s.v" % sys.argv[1], "w") as f: if mode == "test0": io_names = [ "clk", "i0", "o0", "o1", "o2" ] print("module top(input clk, i0, output o0, o1, o2);", file=f) - print(" reg [3:0] state;", file=f) - # print(" always @(posedge clk) state <= (state << 7) ^ (state >> 13) ^ i0;", file=f) - print(" always @(posedge clk) state <= (state << 1) ^ i0;", file=f) - print(" assign o0 = ^state, o1 = |state, o2 = &state;", file=f) + print(" reg [31:0] state;", file=f) + print(" always @(posedge clk) state <= ((state << 5) + state) ^ i0;", file=f) + print(" assign o0 = ^state, o1 = |state, o2 = state[31:16] + state[15:0];", file=f) print("endmodule", file=f) if mode == "test1": io_names = [ "clk", "i0", "i1", "i2", "i3", "o0", "o1", "o2", "o3" ] @@ -42,10 +41,11 @@ with open("%s.ys" % sys.argv[1], "w") as f: print("read_verilog %s_out.v" % sys.argv[1], file=f) print("prep", file=f) print("equiv_make top chip equiv", file=f) - print("hierarchy -top equiv", file=f) + print("cd equiv", file=f) + print("script %s.lc" % sys.argv[1], file=f) print("rename -hide w:N_*", file=f) print("equiv_struct", file=f) - print("opt_clean", file=f) + print("opt_clean -purge", file=f) print("write_ilang %s.il" % sys.argv[1], file=f) print("equiv_status -assert", file=f) @@ -97,6 +97,9 @@ with open("%s_ref.v" % sys.argv[1], "w") as f: f.write(line) +assert os.system("yosys -qp 'select -write %s.lc t:LogicCell40' %s_ref.v" % (sys.argv[1], sys.argv[1])) == 0 +assert os.system(r"sed -i -r 's,.*/(.*)LC_(.*),equiv_add -cell \1LC_\2_gold lc40_\2_gate,' %s.lc" % sys.argv[1]) == 0 + os.remove("%s.bin" % sys.argv[1]) os.remove("%s.vsb" % sys.argv[1]) os.remove("%s.glb" % sys.argv[1]) |