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authorhermitsoft <hermisu@mail.com>2017-03-09 15:23:54 +0100
committerhermitsoft <hermisu@mail.com>2017-03-09 15:23:54 +0100
commitf7334fcf4a1e8779c56ca5d01ed38cb79fd473bf (patch)
treedeb8cd5389761a936251fc5179574f6df8bd493b /icefuzz/make_fflogic.py
parent62b7f71319a73ed10c0428f09e9dae698bdcb116 (diff)
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Maximized icefuzz testcases for LP384-CM49
Diffstat (limited to 'icefuzz/make_fflogic.py')
-rw-r--r--icefuzz/make_fflogic.py4
1 files changed, 2 insertions, 2 deletions
diff --git a/icefuzz/make_fflogic.py b/icefuzz/make_fflogic.py
index ecca7ca..91a5d05 100644
--- a/icefuzz/make_fflogic.py
+++ b/icefuzz/make_fflogic.py
@@ -38,8 +38,8 @@ def print_seq_op(dst, src1, src2, op, f):
for idx in range(num):
with open("work_fflogic/fflogic_%02d.v" % idx, "w") as f:
if os.getenv('ICE384PINS'):
- print("module top(input clk, rst, en, input [1:0] a, b, c, d, output [1:0] y, output z);", file=f)
- print(" reg [1:0] p, q;", file=f)
+ print("module top(input clk, rst, en, input [4:0] a, b, c, d, output [4:0] y, output z);", file=f)
+ print(" reg [4:0] p, q;", file=f)
else:
print("module top(input clk, rst, en, input [15:0] a, b, c, d, output [15:0] y, output z);", file=f)
print(" reg [15:0] p, q;", file=f)