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| author | Tim 'mithro' Ansell <me@mith.ro> | 2018-06-12 17:48:15 -0700 |
|---|---|---|
| committer | Tim 'mithro' Ansell <me@mith.ro> | 2018-06-15 17:04:25 -0700 |
| commit | f1f9da2d5b85b678ead42ff5a4a3d7806be0e706 (patch) | |
| tree | 5a2b705e8eb1d04ebf1d586353a7d6907413aa9b /icebox | |
| parent | 492a337202ee25ae47b4a22c99343d7ae5e40e43 (diff) | |
| download | icestorm-f1f9da2d5b85b678ead42ff5a4a3d7806be0e706.tar.gz icestorm-f1f9da2d5b85b678ead42ff5a4a3d7806be0e706.tar.bz2 icestorm-f1f9da2d5b85b678ead42ff5a4a3d7806be0e706.zip | |
icebox_hlc2asc: Set LUT bits to zero by default.
Diffstat (limited to 'icebox')
| -rwxr-xr-x | icebox/icebox_hlc2asc.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/icebox/icebox_hlc2asc.py b/icebox/icebox_hlc2asc.py index 0506b0f..58164d5 100755 --- a/icebox/icebox_hlc2asc.py +++ b/icebox/icebox_hlc2asc.py @@ -825,7 +825,7 @@ class LogicCell: def __init__(self, tile, index): self.tile = tile self.index = index - self.lut_bits = None + self.lut_bits = ['0'] * 16 self.seq_bits = ['0'] * 4 def read(self, fields): @@ -841,7 +841,7 @@ class LogicCell: if m < 16: lut_bits = (16-m) * "0" + lut_bits # Verilog 16'bXXXX is MSB first but the bitstream wants LSB. - self.lut_bits = lut_bits[::-1] + self.lut_bits = list(lut_bits[::-1]) else: self.lut_bits = logic_expression_to_lut( ' '.join(fields[2:]), ('in_0', 'in_1', 'in_2', 'in_3')) |