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| author | Clifford Wolf <clifford@clifford.at> | 2017-01-09 21:21:15 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-01-09 21:21:15 +0100 |
| commit | f920831e43c686dcaeca39c2481d5f22c014940f (patch) | |
| tree | 8d46f453d511338a1befbbff1ab814caa80b3a2d /examples | |
| parent | ff02cd753c5802c25f770a788eba329ddb668d13 (diff) | |
| download | icestorm-f920831e43c686dcaeca39c2481d5f22c014940f.tar.gz icestorm-f920831e43c686dcaeca39c2481d5f22c014940f.tar.bz2 icestorm-f920831e43c686dcaeca39c2481d5f22c014940f.zip | |
Some cleanups in verilog examples
Diffstat (limited to 'examples')
| -rw-r--r-- | examples/hx8kboard/example.v | 2 | ||||
| -rw-r--r-- | examples/iceblink/example.v | 2 | ||||
| -rw-r--r-- | examples/icestick/example.v | 2 | ||||
| -rw-r--r-- | examples/icezum/example.v | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/examples/hx8kboard/example.v b/examples/hx8kboard/example.v index accbc2e..69a446f 100644 --- a/examples/hx8kboard/example.v +++ b/examples/hx8kboard/example.v @@ -16,7 +16,7 @@ module top ( reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; - always@(posedge clk) begin + always @(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end diff --git a/examples/iceblink/example.v b/examples/iceblink/example.v index 6bccc1e..4642ef2 100644 --- a/examples/iceblink/example.v +++ b/examples/iceblink/example.v @@ -15,7 +15,7 @@ module top ( reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; - always@(posedge clk) begin + always @(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end diff --git a/examples/icestick/example.v b/examples/icestick/example.v index a934400..3eb7007 100644 --- a/examples/icestick/example.v +++ b/examples/icestick/example.v @@ -13,7 +13,7 @@ module top ( reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; - always@(posedge clk) begin + always @(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end diff --git a/examples/icezum/example.v b/examples/icezum/example.v index 9bdf587..1274e69 100644 --- a/examples/icezum/example.v +++ b/examples/icezum/example.v @@ -16,7 +16,7 @@ module top ( reg [BITS+LOG2DELAY-1:0] counter = 0; reg [BITS-1:0] outcnt; - always@(posedge clk) begin + always @(posedge clk) begin counter <= counter + 1; outcnt <= counter >> LOG2DELAY; end |