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author | Clifford Wolf <clifford@clifford.at> | 2017-07-31 14:57:24 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2017-07-31 14:57:24 +0200 |
commit | 872e333cf75c6fc1bdf985f09565c70d16567434 (patch) | |
tree | 11a7b2336faaf12e84d8890c1674c04b0c8093a6 /examples | |
parent | f704149b7298c7c6b56520d104dc4b20abf455b2 (diff) | |
parent | 81e943e050dad652da795d21375bb700064116f4 (diff) | |
download | icestorm-872e333cf75c6fc1bdf985f09565c70d16567434.tar.gz icestorm-872e333cf75c6fc1bdf985f09565c70d16567434.tar.bz2 icestorm-872e333cf75c6fc1bdf985f09565c70d16567434.zip |
Merge branch 'master' into ice5k
Diffstat (limited to 'examples')
-rw-r--r-- | examples/icestick/.gitignore | 14 | ||||
-rw-r--r-- | examples/icestick/Makefile | 16 | ||||
-rw-r--r-- | examples/icestick/checker.v | 55 | ||||
-rw-r--r-- | examples/icestick/checker_tb.v | 40 | ||||
-rw-r--r-- | examples/icestick/rs232demo.v | 8 | ||||
-rw-r--r-- | examples/icestick/rs232demo_tb.v | 74 |
6 files changed, 207 insertions, 0 deletions
diff --git a/examples/icestick/.gitignore b/examples/icestick/.gitignore index 539898f..c854ccc 100644 --- a/examples/icestick/.gitignore +++ b/examples/icestick/.gitignore @@ -6,3 +6,17 @@ rs232demo.bin rs232demo.blif rs232demo.asc rs232demo.rpt +rs232demo_tb +rs232demo_tb.vcd +rs232demo_syn.v +rs232demo_syntb +rs232demo_syntb.vcd +checker.bin +checker.blif +checker.asc +checker.rpt +checker_tb +checker_tb.vcd +checker_syn.v +checker_syntb +checker_syntb.vcd diff --git a/examples/icestick/Makefile b/examples/icestick/Makefile index 9294608..8b8e741 100644 --- a/examples/icestick/Makefile +++ b/examples/icestick/Makefile @@ -1,5 +1,6 @@ PROJ = example # PROJ = rs232demo +# PROJ = checker PIN_DEF = icestick.pcf DEVICE = hx1k @@ -18,6 +19,21 @@ all: $(PROJ).rpt $(PROJ).bin %.rpt: %.asc icetime -d $(DEVICE) -mtr $@ $< +%_tb: %_tb.v %.v + iverilog -o $@ $^ + +%_tb.vcd: %_tb + vvp -N $< +vcd=$@ + +%_syn.v: %.blif + yosys -p 'read_blif -wideports $^; write_verilog $@' + +%_syntb: %_tb.v %_syn.v + iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` + +%_syntb.vcd: %_syntb + vvp -N $< +vcd=$@ + prog: $(PROJ).bin iceprog $< diff --git a/examples/icestick/checker.v b/examples/icestick/checker.v new file mode 100644 index 0000000..a441845 --- /dev/null +++ b/examples/icestick/checker.v @@ -0,0 +1,55 @@ +// A simple circuit that can be used to detect brownouts and other hardware issues + +module top ( + input clk, + output LED1, + output LED2, + output LED3, + output LED4, + output LED5 +); + reg [7:0] reset_counter = 0; + reg resetn = 0; + + always @(posedge clk) begin + reset_counter <= reset_counter + 1; + resetn <= resetn | &reset_counter; + end + + reg error, rdmode, rdfin; + + reg [31:0] scratchpad [0:1023]; + reg [31:0] xorshift32_state; + reg [9:0] index; + + reg [31:0] next_xorshift32_state; + + always @* begin + next_xorshift32_state = xorshift32_state ^ ( xorshift32_state << 13); + next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state >> 17); + next_xorshift32_state = next_xorshift32_state ^ (next_xorshift32_state << 5); + end + + always @(posedge clk) begin + xorshift32_state <= &index ? 123456789 : next_xorshift32_state; + index <= index + 1; + + if (!resetn) begin + xorshift32_state <= 123456789; + index <= 0; + error <= 0; + rdmode <= 0; + rdfin <= 0; + end else + if (!rdmode) begin + scratchpad[index] <= xorshift32_state; + rdmode <= &index; + end else begin + if (scratchpad[index] != xorshift32_state) error <= 1; + rdfin <= rdfin || &index; + end + end + + wire ok = resetn && rdfin && !error; + assign LED1 = 0, LED2 = error, LED3 = 0, LED4 = error, LED5 = ok; +endmodule diff --git a/examples/icestick/checker_tb.v b/examples/icestick/checker_tb.v new file mode 100644 index 0000000..241c89e --- /dev/null +++ b/examples/icestick/checker_tb.v @@ -0,0 +1,40 @@ +module testbench; + reg clk; + always #5 clk = (clk === 1'b0); + + wire ok; + + top uut ( + .clk(clk), + .LED5(ok) + ); + + reg [4095:0] vcdfile; + + initial begin + if ($value$plusargs("vcd=%s", vcdfile)) begin + $dumpfile(vcdfile); + $dumpvars(0, testbench); + end + end + + initial begin + @(posedge ok); + @(negedge ok); + $display("ERROR: detected falling edge on OK pin!"); + $stop; + end + + initial begin + repeat (3000) @(posedge clk); + + if (!ok) begin + $display("ERROR: OK pin not asserted after 3000 cycles!"); + $stop; + end + + repeat (10000) @(posedge clk); + $display("SUCCESS: OK pin still asserted after 10000 cycles."); + $finish; + end +endmodule diff --git a/examples/icestick/rs232demo.v b/examples/icestick/rs232demo.v index f9e7546..40347e8 100644 --- a/examples/icestick/rs232demo.v +++ b/examples/icestick/rs232demo.v @@ -19,6 +19,14 @@ module top ( reg [3:0] bit_cnt = 0; reg recv = 0; + initial begin + LED1 = 0; + LED2 = 0; + LED3 = 0; + LED4 = 0; + LED5 = 0; + end + always @(posedge clk) begin buffer_valid <= 0; if (!recv) begin diff --git a/examples/icestick/rs232demo_tb.v b/examples/icestick/rs232demo_tb.v new file mode 100644 index 0000000..5b9aee1 --- /dev/null +++ b/examples/icestick/rs232demo_tb.v @@ -0,0 +1,74 @@ +module testbench; + localparam integer PERIOD = 12000000 / 9600; + + // reg clk = 0; + // initial #10 forever #5 clk = ~clk; + + reg clk; + always #5 clk = (clk === 1'b0); + + reg RX = 1; + wire TX; + wire LED1; + wire LED2; + wire LED3; + wire LED4; + wire LED5; + + top uut ( + .clk (clk ), + .RX (RX ), + .TX (TX ), + .LED1(LED1), + .LED2(LED2), + .LED3(LED3), + .LED4(LED4), + .LED5(LED5) + ); + + task send_byte; + input [7:0] c; + integer i; + begin + RX <= 0; + repeat (PERIOD) @(posedge clk); + + for (i = 0; i < 8; i = i+1) begin + RX <= c[i]; + repeat (PERIOD) @(posedge clk); + end + + RX <= 1; + repeat (PERIOD) @(posedge clk); + end + endtask + + reg [4095:0] vcdfile; + + initial begin + if ($value$plusargs("vcd=%s", vcdfile)) begin + $dumpfile(vcdfile); + $dumpvars(0, testbench); + end + + repeat (10 * PERIOD) @(posedge clk); + + // turn all LEDs on + send_byte("1"); + send_byte("2"); + send_byte("3"); + send_byte("4"); + send_byte("5"); + + // turn all LEDs off + send_byte("1"); + send_byte("2"); + send_byte("3"); + send_byte("4"); + send_byte("5"); + + repeat (10 * PERIOD) @(posedge clk); + + $finish; + end +endmodule |