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authorClaire Wolf <clifford@clifford.at>2020-06-25 18:35:48 +0200
committerGitHub <noreply@github.com>2020-06-25 18:35:48 +0200
commitf138ade065c4893e2dd0460ba4abbe13922aa47b (patch)
tree37539539e6132b524b48187a7b7331cc994e32f4
parent9e44d9f1d2d49ed191bb7793f012ef523ad7f350 (diff)
parentce1d811d21fa40acbe7a772b3b53dafe3a7dfae0 (diff)
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Merge pull request #257 from smunaut/ice40_shiftreg_div_mode
icebox: Add support for the bit 1 of SHIFTREG_DIV_MODE
-rw-r--r--icebox/icebox.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/icebox/icebox.py b/icebox/icebox.py
index 0422f13..ab83fd0 100644
--- a/icebox/icebox.py
+++ b/icebox/icebox.py
@@ -1954,7 +1954,8 @@ pllinfo_db = {
"PLLOUT_SELECT_B_1": (12, 31, "PLLCONFIG_3"),
# Numeric Parameters
- "SHIFTREG_DIV_MODE": (12, 31, "PLLCONFIG_4"),
+ "SHIFTREG_DIV_MODE_0": (12, 31, "PLLCONFIG_4"),
+ "SHIFTREG_DIV_MODE_1": (14, 31, "PLLCONFIG_6"),
"FDA_FEEDBACK_0": (12, 31, "PLLCONFIG_9"),
"FDA_FEEDBACK_1": (13, 31, "PLLCONFIG_1"),
"FDA_FEEDBACK_2": (13, 31, "PLLCONFIG_2"),