Update index.html

Signed-off-by: Claire Wolf <claire@symbioticeda.com>

1 files changed, 10 insertions, 8 deletions

diff --git a/docs/index.html b/docs/index.html
index 3ca1721..fc50ea8 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -30,7 +30,7 @@
 <h2>What is Project IceStorm?</h2>
 
 <p>
-Project IceStorm aims at reverse engineering and documenting the bitstream
+Project IceStorm aims at documenting the bitstream
 format of Lattice iCE40 FPGAs and providing simple tools for analyzing and
 creating bitstream files. The IceStorm flow (<a
 href="http://www.clifford.at/yosys/">Yosys</a>, <a
@@ -49,8 +49,8 @@ and UltraLite parts are not yet supported.
 
 <p>
 It has a very minimalistic architecture with a very regular structure. There are not many
-different kinds of tiles or special function units. This makes it both ideal for
-reverse engineering and as a reference platform for general purpose FPGA tool development.
+different kinds of tiles or special function units. This makes it both ideal for creating
+bitstream documentations and as a reference platform for general purpose FPGA tool development.
 </p>
 
 <p>
@@ -64,8 +64,8 @@ Breakout Board</a> featuring an HX8K chip.)
 <h2>What is the Status of the Project?</h2>
 
 <p>
-We are pretty confident that we have the 1K and 8K devices completely reverse
-engineered. For example, it seems we can create correct functional Verilog
+We are pretty confident that we have the 1K and 8K devices completely
+documented. For example, it seems we can create correct functional Verilog
 models for all bitstreams generated by Lattice iCEcube2 for the iCE40
 HX1K-TQ144 and the iCE40 HX8K-CT256 using our <tt>icebox_vlog</tt> tool.
 </p>
@@ -557,12 +557,14 @@ Links to related projects. Contact me at clifford@clifford.at if you have an int
 <li><a href="http://hedmen.org/icestorm-doc/icestorm.html">IceStorm Learner’s Documentation</a>
 </ul>
 
-<h3>Other FPGA reverse engineering projects</h3>
+<h3>Other FPGA bitstream documentation projects</h3>
 
 <ul>
-<li><a href="https://github.com/Wolfgang-Spraul/fpgatools">Xilinx xc6slx9 reverse engineering, Wolfgang Spraul</a>
+<li><a href="https://github.com/SymbiFlow/prjtrellis">ECP5 bitstream documentation (Project Trellis)</a>
+<li><a href="https://github.com/SymbiFlow/prjxray">Xilinx 7-series bitstream documentation (Project X-Ray)</a>
+<li><a href="https://github.com/Wolfgang-Spraul/fpgatools">Xilinx xc6slx9 documentation, Wolfgang Spraul</a>
 <li><a href="http://www.fabienm.eu/flf/wp-content/uploads/2014/11/Note2008.pdf">From the bitstream to the netlist, Jean-Baptiste Note and Éric Rannaud</a>
-<li><a href="http://git.bfuser.eu/?p=marex/typhoon.git;a=commit">Cyclone IV EP4CE6 reverse engineering, Marek Vasut</a>
+<li><a href="http://git.bfuser.eu/?p=marex/typhoon.git;a=commit">Cyclone IV EP4CE6 documentation, Marek Vasut</a>
 </ul>
 
 <hr>