testsuite/vests/vhdl-93/clifton-labs/compliant/functional/variable/simple-enumeration-assign.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

entity foo is
end foo;

use std.textio.all;

architecture only of foo is
begin  -- only
  process
    variable x : boolean := false;
  begin  -- process
    x := true;
    assert x = true report "TEST FAILED - x does not equal true" severity failure;
    assert x /= true report "TEST PASSED" severity note;
    wait;
  end process;
end only;