testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

entity test_bench is
end test_bench;

architecture only of test_bench is
  signal sig : integer := 0;
begin  -- only
  assign: process
  begin  -- process p
    sig <= 1;
    wait;
  end process assign;

  check1: process
  begin  -- process check1
    wait for 1 fs;
    assert sig = 1 report "TEST FAILED" severity FAILURE;
    wait;
  end process check1;

  check2: process
  begin  -- process check1
    wait for 1 fs;
    assert sig = 1 report "TEST FAILED" severity FAILURE;
    wait;
  end process check2;

  check3: process
  begin  -- process check1
    wait for 2 fs;
    report "TEST PASSED" severity NOTE;
    wait;
  end process check3;

  
end only;