aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc779.vhd
blob: db64d42b7c98b8d1d418ff18e319b2670d6e799f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
-- Copyright (C) 2001 Bill Billowitch.

-- Some of the work to develop this test suite was done with Air Force
-- support.  The Air Force and Bill Billowitch assume no
-- responsibilities for this software.

-- This file is part of VESTs (Vhdl tESTs).

-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version. 

-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for more details. 

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: tc779.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------

ENTITY c01s01b01x02p11n02i00779ent_a IS
  port (c2 : buffer Bit);
END c01s01b01x02p11n02i00779ent_a;

ARCHITECTURE c01s01b01x02p11n02i00779arch_a OF c01s01b01x02p11n02i00779ent_a IS
BEGIN
END c01s01b01x02p11n02i00779arch_a;



ENTITY c01s01b01x02p11n02i00779ent IS
  port(P2 : buffer Bit);
END c01s01b01x02p11n02i00779ent;

ARCHITECTURE c01s01b01x02p11n02i00779arch OF c01s01b01x02p11n02i00779ent IS
  component c01s01b01x02p11n02i00779ent_b
    port (C2 : buffer Bit);
  end component;
  for L : c01s01b01x02p11n02i00779ent_b use entity work.c01s01b01x02p11n02i00779ent(c01s01b01x02p11n02i00779arch) port map (C2);
BEGIN

  L : c01s01b01x02p11n02i00779ent_b port map (C2 => P2);

  TEST : Process
  begin
    P2 <= bit'('1');
    wait for 15 ns;
  end process TEST;

  TESTING: PROCESS
  BEGIN
    P2 <= bit'('0');   -- Failure_here
    -- This error will be indicated at elaboration time.
    wait for 11 ns;
    assert FALSE
      report "***FAILED TEST: c01s01b01x02p11n02i00779 - Actual can have at most one source."
      severity ERROR;
    wait;
  END PROCESS TESTING;

END c01s01b01x02p11n02i00779arch;