1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc878.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s01b00x00p03n01i00878pkg is
constant UNIT_DELAY: TIME := 1 ns;
end c10s01b00x00p03n01i00878pkg;
-- a nand gate
entity ENT1 is
port ( BITIN1, BITIN2 : in BIT;
BITOUT: out BIT );
end ENT1;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
architecture ARC1 of ENT1 is
begin
BITOUT <= ( BITIN1 nand BITIN2 ) after UNIT_DELAY;
end ARC1;
configuration CON1 of ENT1 is
for ARC1
end for;
end CON1;
-- build an inverter from nand-nand logic
entity ENT2 is
port ( GOING_IN: in BIT;
COMING_OUT: out BIT );
end ENT2;
architecture ARC2 of ENT2 is
component NAND_BOX
port ( IN1, IN2: in BIT; OUT1: out BIT );
end component;
signal STUCKAT_HIGH: BIT := '1';
begin
NAND_COMP: NAND_BOX port map ( GOING_IN, STUCKAT_HIGH, COMING_OUT );
end ARC2;
use WORK.CON1;
configuration CON2 of ENT2 is
for ARC2
for NAND_COMP: NAND_BOX
use configuration CON1
port map ( IN1, IN2, OUT1 );
end for;
end for;
end CON2;
-- declare a test bench
ENTITY c10s01b00x00p03n01i00878ent IS
END c10s01b00x00p03n01i00878ent;
use WORK.c10s01b00x00p03n01i00878pkg.UNIT_DELAY;
ARCHITECTURE c10s01b00x00p03n01i00878arch OF c10s01b00x00p03n01i00878ent IS
component INV
port ( ENTRA: in BIT; SALE: out BIT );
end component;
signal SIGIN, SIGOUT: BIT;
BEGIN
INVERTER: INV port map ( SIGIN, SIGOUT );
TESTING: PROCESS
variable k : integer := 0;
BEGIN
SIGIN <= '0';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '1') then
k := 1;
end if;
assert ( SIGOUT = '1' )
report "didn't invert low to high" severity FAILURE;
wait for ( 3 * UNIT_DELAY );
SIGIN <= '1';
wait for ( 2 * UNIT_DELAY );
if (SIGOUT /= '0') then
k := 1;
end if;
assert ( SIGOUT = '0' )
report "didn't invert high to low" severity FAILURE;
assert NOT( k=0 )
report "***PASSED TEST: c10s01b00x00p03n01i00878"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c10s01b00x00p03n01i00878 - A declartive region is formed by the text of a configuration declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s01b00x00p03n01i00878arch;
use WORK.CON2;
configuration c10s01b00x00p03n01i00878cfg of c10s01b00x00p03n01i00878ent is
for c10s01b00x00p03n01i00878arch
for INVERTER: INV
use configuration CON2
port map ( ENTRA, SALE );
end for;
end for;
end c10s01b00x00p03n01i00878cfg;
|
