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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc483.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00483ent IS
END c03s02b01x01p19n01i00483ent;
ARCHITECTURE c03s02b01x01p19n01i00483arch OF c03s02b01x01p19n01i00483ent IS
type record_std_package is record
a:boolean;
b:bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9);
type array_rec_std is array (integer range <>) of record_std_package;
function resolution10(i:in array_rec_std) return record_std_package is
variable temp : record_std_package := C50;
begin
return temp;
end resolution10;
subtype array_rec_std_state is resolution10 record_std_package;
constant C66 : array_rec_std_state := C50;
function complex_scalar(s : array_rec_std_state) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return array_rec_std_state is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : array_rec_std_state;
signal S2 : array_rec_std_state;
signal S3 : array_rec_std_state:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00483"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00483 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00483arch;
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