aboutsummaryrefslogtreecommitdiffstats
path: root/testsuite/vests/vhdl-93/billowitch/compliant/tc2966.vhd
blob: 19e38639d9a3ba47183dbe6dad98c5539ed3282a (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
-- Copyright (C) 2001 Bill Billowitch.

-- Some of the work to develop this test suite was done with Air Force
-- support.  The Air Force and Bill Billowitch assume no
-- responsibilities for this software.

-- This file is part of VESTs (Vhdl tESTs).

-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version. 

-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-- for more details. 

-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 

-- ---------------------------------------------------------------------
--
-- $Id: tc2966.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------

ENTITY c02s03b01x00p01n01i02966ent IS
END c02s03b01x00p01n01i02966ent;

ARCHITECTURE c02s03b01x00p01n01i02966arch OF c02s03b01x00p01n01i02966ent IS

BEGIN
  TESTING: PROCESS
    function "and" (a, b: in integer) return boolean is
    begin
      return false;
    end;
    variable i1, i2    :integer := 2;
    variable b1, b2    :boolean := true;
    variable q1      :boolean ;
    variable q2      :boolean ;
    variable q3      :boolean ;
  BEGIN
    q1 := i1 and i2;
    q2 := b1 and b2;
    q3 := "and" (i1, i2);
    wait for 5 ns;
    assert NOT( q1=false and q2=true and q3=false )
      report "***PASSED TEST: c02s03b01x00p01n01i02966"
      severity NOTE;
    assert ( q1=false and q2=true and q3=false )
      report "***FAILED TEST: c02s03b01x00p01n01i02966 - Function overload test failed."
      severity ERROR;
    wait;
  END PROCESS TESTING;

END c02s03b01x00p01n01i02966arch;