1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_18_ch_18_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_18_02_a is
end entity ch_18_02_a;
architecture writer of ch_18_02_a is
begin
process is
type bit_vector_file is file of bit_vector;
file vectors : bit_vector_file open write_mode is "vectors.dat";
begin
write(vectors, bit_vector'(""));
write(vectors, bit_vector'("1"));
write(vectors, bit_vector'("10"));
write(vectors, bit_vector'("011"));
write(vectors, bit_vector'("0100"));
write(vectors, bit_vector'("00101"));
write(vectors, bit_vector'("000110"));
write(vectors, bit_vector'("0000111"));
write(vectors, bit_vector'("00001000"));
write(vectors, bit_vector'("111111111111111111111111111111111111111111111111111111111111111111111111"));
wait;
end process;
end architecture writer;
----------------------------------------------------------------
entity ch_18_02 is
end entity ch_18_02;
----------------------------------------------------------------
architecture test of ch_18_02 is
begin
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
type bit_vector_file is file of bit_vector;
procedure read ( file f : file_type;
value : out element_type; length : out natural );
-- end of code from book
procedure read ( file f : file_type;
value : out element_type; length : out natural ) is
begin
end;
-- end of code from book
begin
wait;
end process;
process is
type bit_vector_file is file of bit_vector;
-- code from book:
file vectors : bit_vector_file open read_mode is "vectors.dat";
variable next_vector : bit_vector(63 downto 0);
variable actual_len : natural;
-- end of code from book
variable lost : boolean;
begin
while not endfile(vectors) loop
-- code from book:
read(vectors, next_vector, actual_len);
-- end of code from book
lost :=
-- code from book:
actual_len > next_vector'length
-- end of code from book
;
end loop;
wait;
end process;
end architecture test;
|
