1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_13.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity ms_flipflop is
port ( phi1, phi2 : in std_logic;
d : in std_logic;
q : out std_logic );
end entity ms_flipflop;
architecture normal_drive of ms_flipflop is
signal master_d : std_logic;
begin
master_d <= d when phi1 = '1';
q <= master_d when phi2 = '1';
end architecture normal_drive;
architecture high_drive of ms_flipflop is
signal master_d : std_logic;
begin
master_d <= d when phi1 = '1';
q <= master_d when phi2 = '1';
end architecture high_drive;
-- code from book
library cell_lib;
configuration last_high_drive of shift_reg is
for cell_level
-- workaround for MTI bug mt026
-- for reg_array ( 0 to parallel_data'length - 2 )
for reg_array ( 0 to 2 )
-- end workaround
for first_cell
for cell : master_slave_flipflop
use entity cell_lib.ms_flipflop(normal_drive);
end for;
end for;
for other_cell
for cell : master_slave_flipflop
use entity cell_lib.ms_flipflop(normal_drive);
end for;
end for;
end for;
-- workaround for MTI bug mt026
-- for reg_array ( parallel_data'length - 1 )
for reg_array ( 3 )
-- end workaround
for other_cell
for cell : master_slave_flipflop
use entity cell_lib.ms_flipflop(high_drive);
end for;
end for;
end for;
end for;
end configuration last_high_drive;
-- end code from book
library ieee; use ieee.std_logic_1164.all;
entity fg_14_13 is
end entity fg_14_13;
architecture test of fg_14_13 is
signal phi1, phi2, serial_data_in : std_logic := '0';
signal parallel_data : std_logic_vector(3 downto 0);
begin
dut : configuration work.last_high_drive
port map ( phi1 => phi1, phi2 => phi2,
serial_data_in => serial_data_in,
parallel_data => parallel_data );
clock_gen : process is
begin
phi1 <= '1', '0' after 4 ns;
phi2 <= '1' after 5 ns, '0' after 9 ns;
wait for 10 ns;
end process clock_gen;
stimulus : process is
begin
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0';
wait;
end process stimulus;
end architecture test;
|
