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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_09_fg_09_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package fg_09_02_a is
-- code from book (in text)
function "+" ( bv1, bv2 : bit_vector ) return bit_vector;
-- end code from book
end package fg_09_02_a;
package body fg_09_02_a is
-- code from book
function "+" ( bv1, bv2 : bit_vector ) return bit_vector is
alias norm1 : bit_vector(1 to bv1'length) is bv1;
alias norm2 : bit_vector(1 to bv2'length) is bv2;
variable result : bit_vector(1 to bv1'length);
variable carry : bit := '0';
begin
if bv1'length /= bv2'length then
report "arguments of different length" severity failure;
else
for index in norm1'reverse_range loop
result(index) := norm1(index) xor norm2(index) xor carry;
carry := ( norm1(index) and norm2(index) )
or ( carry and ( norm1(index) or norm2(index) ) );
end loop;
end if;
return result;
end function "+";
-- end code from book
end package body fg_09_02_a;
entity fg_09_02_b is
end entity fg_09_02_b;
architecture test of fg_09_02_b is
use work.fg_09_02_a.all;
begin
stimulus : process is
use std.textio.all;
variable L : line;
begin
write(L, X"0002" + X"0000");
writeline(output, L);
write(L, X"0002" + X"0005");
writeline(output, L);
write(L, X"0002" + X"FFFE");
writeline(output, L);
wait;
end process stimulus;
end architecture test;
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