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library ieee;
use ieee.std_logic_1164.all;
entity unaries is
port (
l4 : std_logic_vector (3 downto 0);
plus_v : out std_logic_vector (3 downto 0);
minus_v : out std_logic_vector (3 downto 0);
abs_v : out std_logic_vector (3 downto 0));
end unaries;
library ieee;
use ieee.std_logic_unsigned.all;
architecture behav of unaries is
begin
plus_v <= +l4;
-- Dummy for compatibility with signed operations.
minus_v <= not l4;
abs_v <= +l4;
end behav;
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