blob: 0dc38287127b0f76171d23ed4b03e58cfb188dcd (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Srot01 is
port(
v : in signed(7 downto 0);
ro : out signed(7 downto 0);
lo : out signed(7 downto 0)
);
end Srot01;
architecture rtl of Srot01 is
begin
ro <= v ror 1;
lo <= v rol 1;
end rtl;
|