testsuite/synth/issue945/syn_ent.vhdl


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entity ent is
end ent;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

architecture rtl of ent is
  signal test : std_logic;
begin
  -- ent.vhdl:5:12
  test <= <unassigned>; -- (signal)
end rtl;