testsuite/synth/issue2124/b.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

library ieee;
use ieee.std_logic_1164.all;

entity b is
  port (
    c : in  std_logic;
    d : in  std_logic;
    q : out std_logic
    );
end entity;

architecture behaviour of b is
begin

  process (c)
  begin
    if rising_edge(c)
    then
      q <= d;
    end if;
  end process;
  
end architecture;