blob: 82f8039cd664c80861e5840b0b22fd0a17a16969 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
|
library IEEE;
use IEEE.std_logic_1164.all;
entity a is
port(
irq : out std_ulogic
);
end a;
library IEEE;
use IEEE.std_logic_1164.all;
entity b is
generic(
NUM_CHANNELS : positive := 4
);
port(
src_channel : in integer range 0 to NUM_CHANNELS-1;
src_valid : in std_ulogic;
src_ready : out std_ulogic
);
end b;
architecture struct of a is
signal src_valid : std_ulogic;
signal src_ready : std_ulogic;
begin
u0 : entity work.b
generic map(
NUM_CHANNELS => 1
)
port map(
src_channel => 0,
src_valid => src_valid,
src_ready => src_ready
);
end architecture;
architecture behav of b is
begin
process(all)
variable ready : std_ulogic;
variable channel_ready : std_ulogic;
begin
ready := '1';
for i in 0 to NUM_CHANNELS-1 loop
if i = src_channel and src_valid = '1' then
channel_ready := '0';
else
channel_ready := '1';
end if;
ready := ready and channel_ready;
end loop;
src_ready <= ready;
end process;
end architecture;
|
