blob: d8649301af580af256747edcb43eaef0f5e8c82c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
library ieee;
use ieee.std_logic_1164.all;
entity issue is
port (
clk : in std_logic
);
end entity issue;
architecture psl of issue is
attribute anyconst : boolean;
signal a: natural;
attribute anyconst of a : signal is true;
begin
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- works
assume always a = 42;
assert always a = 42;
end architecture;
|
