blob: 5d07333556fddb12b1e8886f6e3e31388459f5a4 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
library ieee;
use ieee.std_logic_1164.all;
entity dummy_sub is
port (
clk : in std_logic;
dummy : out std_logic
);
end entity;
architecture a of dummy_sub is
signal first_cycle : std_logic := '1';
begin
support : process
begin
wait until rising_edge(clk);
dummy <= '0';
assert clk = '0';
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity dummy_top is
port(
clk : in std_logic;
dummy : out std_logic
);
end entity;
architecture a of dummy_top is
begin
------------------------------------------------------------------------------
dummy_sub_inst : entity work.dummy_sub
port map(
clk => clk,
dummy => open -- Connecting dummy here triggers instantiation of dummy_sub
);
end architecture;
|
