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library ieee;
use ieee.std_logic_1164.all;
entity repro2 is
port (a : out std_logic;
b : std_logic_vector(7 downto 0));
end;
architecture behav of repro2 is
signal s : std_logic_vector(7 downto 0);
begin
s <= b;
a <= '1' when s /= x"00" else '0';
s (0) <= '0';
end behav;
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