blob: 31568145a289fab2346e12d9807961689d210110 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
|
library ieee;
use ieee.std_logic_1164.all;
entity assert3 is
port (v : std_logic_Vector (7 downto 0);
en : std_logic;
res : out natural);
end;
architecture behav of assert3 is
begin
process (v, en)
begin
res <= 0;
if en = '1' then
for i in v'range loop
if v (i) = '1' then
res <= i;
exit;
end if;
assert i > 3 report "bad v value";
end loop;
end if;
end process;
end behav;
|
