blob: 6a521008c391f2e03d1f3ee90c44df91d1891954 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity issue1 is
port(
a : in std_logic_vector(7 downto 0);
b : out std_logic_vector(2 downto 0)
);
end issue1;
architecture behavior of issue1 is
begin
b <= std_logic_vector(unsigned(a) + 1);
end behavior;
|
