blob: 7492e36c9171ad3e8ecedb43e6fee3a483baecdf (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
entity repro2 is
port (clk : bit;
rst : bit;
d : bit;
q : out bit);
end repro2;
architecture behav of repro2 is
constant c : bit := '1';
signal s : bit := c;
begin
process (clk)
begin
if rst = '1' then
s <= c;
elsif clk = '1' and clk'event then
s <= d;
end if;
end process;
q <= s;
end behav;
|
