blob: 229dcf17c1f51d847824c231aaa41928981c8045 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
|
entity tb_repro3_1 is
end tb_repro3_1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro3_1 is
signal clk : std_logic;
signal led : std_logic_vector(7 downto 0);
begin
dut: entity work.repro3_1
port map (clk, led);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
pulse;
assert led = x"01" severity failure;
pulse;
assert led = x"02" severity failure;
wait;
end process;
end behav;
|
