testsuite/synth/issue1080/repro.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

entity repro_sub is
  generic (
    val : natural := 10);
  port (
    a : natural := val;
    b : out natural);
end repro_sub;

architecture behav of repro_sub is
begin
  b <= a + 1;
end behav;

entity repro is
  port (
    a : natural;
    b : out natural);
end repro;

architecture rtl of repro is
begin
  dut: entity work.repro_sub
    port map (b => b);
end rtl;