testsuite/synth/issue1035/ent.vhdl


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library ieee;
use ieee.std_logic_1164.all;

entity ent is
end ent;

architecture a of ent is
	constant c : std_logic_vector(7 downto 0) := x"00";
begin
	process(all)
	begin
		case c is
			when others =>
		end case;
	end process;
end a;