blob: 69ac5a3e1ea0f90c87c7f7a9a55bfe12b13145c2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
|
entity gen_delay is
generic (type T);
port (i : in T;
o : out T);
end gen_delay;
architecture arch of gen_delay is
begin
o <= i;
end arch;
entity dly1 is
port (i : in bit;
o : out bit);
end dly1;
architecture struct of dly1 is
begin
inst: entity work.gen_delay
generic map (T => bit)
port map (i => i, o => o);
end struct;
|
