testsuite/synth/dispvhdl01/vhd01.vhdl


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library ieee;
use ieee.std_logic_1164.all;
use work.pkg.all;

entity vhd01 is
  port (i1 : std_logic_vector (1 to 1);
        o1 : out std_logic_vector (1 to 1));
end vhd01;

architecture behav of vhd01 is
begin
  o1 <= i1;
end behav;