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library ieee;
use ieee.std_logic_1164.all;
entity dff02 is
port (q : out std_logic;
d : std_logic;
clk : std_logic;
rst : std_logic);
end dff02;
architecture behav of dff02 is
begin
q <= '0' when rst = '1' else d when rising_edge (clk);
end behav;
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