testsuite/synth/dff05/dff01.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13

library ieee;
use ieee.std_logic_1164.all;

entity dff01 is
  port (q : out std_logic;
        d : std_logic;
        clk : std_logic);
end dff01;

architecture behav of dff01 is
begin
  q <= d when rising_edge (clk);
end behav;