blob: 0d8eaf67d184ac70571a14a133c5225906091e98 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
|
library ieee;
use ieee.std_logic_1164.all;
entity dff02 is
port (q : out std_logic;
d : std_logic;
clk : std_logic;
rstn : std_logic);
end dff02;
architecture behav of dff02 is
begin
process (clk, rstn) is
begin
if rstn = '0' then
q <= '0';
elsif rising_edge (clk) then
q <= d;
end if;
end process;
end behav;
|
