entity t5 is end t5; library ieee; use ieee.std_logic_1164.all; architecture behav of t5 is signal s : std_logic := '0'; begin b: block port (p : out std_logic := 'Z'); port map (p => s); begin end block; b2: block port (p : out std_logic := '1'); port map (p => s); begin end block; process begin wait for 1 ns; assert s = 'X' severity failure; wait; end process; end behav; ' href='ssh://git@git.panaceas.org/git/iCE40/ghdl' title='iCE40/ghdl Git repository'/>
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path: root/testsuite/synth/comp03/comp03.vhdl
blob: 6a8a23b4d353f8f5cbffb1aebddf32a5dc731cba (plain) 
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library ieee;
use ieee.std_logic_1164.all;

entity comp03 is
  port (p : std_logic_vector (6 downto 0);
        o : out std_logic);
end comp03;

architecture behav of comp03 is
begin
  inst: entity work.sub1
    port map (p => p, o => o);
end behav;
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-06 07:35:29 +0000